Semiconductor wafer mass metrology apparatus and semiconductor wafer mass metrology method
Granted: April 29, 2025
Patent Number:
12288702
A semiconductor wafer mass metrology apparatus comprising: a measurement chamber for measuring the weight and/or the mass of a semiconductor wafer; a first temperature changing part for changing a temperature of the semiconductor wafer before the semiconductor wafer is transported into the measurement chamber; and a first temperature sensor for sensing a first temperature, wherein the first temperature is: a temperature of the first temperature changing part; or a temperature of the…
Modifying hydrophobicity of a wafer surface using an organosilicon precursor
Granted: April 29, 2025
Patent Number:
12288685
Methods and apparatuses for modifying a wafer surface using an organosilicon precursor are provided herein. The wafer surface is dosed with the organosilicon precursor following deposition of a dielectric material by an atomic layer deposition (ALD) process. In some implementations, the dielectric layer is made of silicon oxide. Dosing the wafer surface with the organosilicon precursor may occur in the same chamber as the ALD process. The organosilicon precursor may modify the wafer…
Plasma-enhanced atomic layer deposition with radio-frequency power ramping
Granted: April 8, 2025
Patent Number:
12270103
Methods and apparatuses for depositing thin films using plasma-enhanced atomic layer deposition (PEALD) with ramping radio-frequency (RF) power are provided herein. Embodiments involve increasing the RF power setting of PEALD cycles after formation of initial screening layers at low RF power settings.
Line bending control for memory applications
Granted: April 8, 2025
Patent Number:
12274047
A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation…
Station-to-station control of backside bow compensation deposition
Granted: April 8, 2025
Patent Number:
12272608
Methods for reducing warpage of bowed semiconductor substrates, including providing a first substrate to a first station in a semiconductor processing chamber, providing a second substrate to a second station in the semiconductor processing chamber, concurrently depositing a first bow compensation layer of material on the backside of the first substrate at the first station and a first bow compensation layer of material on the backside of the second substrate at the second station, and…
Friction stir welding in semiconductor manufacturing applications
Granted: April 8, 2025
Patent Number:
12272591
In an example, a showerhead pedestal assembly for a substrate processing chamber is provided. The showerhead pedestal assembly includes a faceplate. A platen is disposed within the faceplate and includes a heater element extending through at least one groove in the faceplate. The at least one groove is profiled to accept at least one portion of the heater element. A periphery of the platen is joined to an interior surface of the faceplate by a friction stir welded joint.
Reduced footprint wafer handling platform
Granted: April 8, 2025
Patent Number:
12272583
A system comprises an equipment front end module (EFEM), a vacuum transfer module (VTM), a plurality off quad station process modules (QSMs). The EFEM is configured to receive a plurality of wafers. The EFEM comprises an EFEM transfer robot. The vacuum transfer module (VTM) is configured to receive the plurality of wafers from the EFEM. The VTM comprises a VTM transfer robot. The plurality of quad station process modules (QSMs) is coupled to the VTM. The VTM transfer robot is configured…
Systems and methods for metastable activated radical selective strip and etch using dual plenum showerhead
Granted: April 8, 2025
Patent Number:
12272571
Several designs of a gas distribution device for a substrate processing system are provided. The gas distribution device includes a dual plenum showerhead. Additionally, designs for a light blocking structure used with the showerheads are also provided.
Systems and methods for metastable activated radical selective strip and etch using dual plenum showerhead
Granted: April 8, 2025
Patent Number:
12272570
Several designs of a gas distribution device for a substrate processing system are provided. The gas distribution device includes a dual plenum showerhead. Additionally, designs for a light blocking structure used with the showerheads are also provided.
Method and apparatus for measuring particles
Granted: April 8, 2025
Patent Number:
12270748
An apparatus for measuring contamination on a critical surface of a part is provided. A vessel for mounting the part is provided. An inert gas source is in fluid connection with the vessel and adapted to provide an inert gas to the vessel. At least one diffuser receives the inert gas from the vessel, wherein the critical surface of the part is exposed to the inert gas when the part is mounted in the vessel. At least one analyzer is adapted to receive inert gas from the at least one…
Thermoelectric cooling pedestal for substrate processing systems
Granted: April 1, 2025
Patent Number:
12266588
A temperature-controlled pedestal includes a pedestal, a temperature sensor to sense N temperature in N zones, and N temperature control devices arranged in the N zones, respectively. A voltage source selectively supplies power to the N temperature control devices. A controller is configured to cause the voltage source to control a temperature in the N zones by a) determining a hottest one of the N zones based on the N temperatures; b) if the hottest one of the N zones is not already…
Atomic layer etching for subtractive metal etch
Granted: April 1, 2025
Patent Number:
12266542
A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by…
Systems and methods for using binning to increase power during a low frequency cycle
Granted: April 1, 2025
Patent Number:
12266505
A method for achieving uniformity in an etch rate is described. The method includes receiving a voltage signal from an output of a match, and determining a positive crossing and a negative crossing of the voltage signal for each cycle of the voltage signal. The negative crossing of each cycle is consecutive to the positive crossing of the cycle. The method further includes dividing a time interval of each cycle of the voltage signal into a plurality of bins. For one or more of the…
Inlet adapter component
Granted: April 1, 2025
Patent Number:
D1069043
Tungsten feature fill with inhibition control
Granted: March 25, 2025
Patent Number:
12261081
Methods for selective inhibition control in semiconductor manufacturing are provided. An example method includes providing a substrate including a feature having one or more feature openings and a feature interior. A nucleation layer is formed on a surface of the feature interior. Based on a differential inhibition profile, a nonconformal bulk layer is selectively formed on a surface of the nucleation layer to leave a region of the nucleation layer covered, and a region of the nucleation…
Multi-layer hardmask for defect reduction in EUV patterning
Granted: March 25, 2025
Patent Number:
12261044
Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer…
Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
Granted: March 25, 2025
Patent Number:
12261038
Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be…
Protection system for switches in direct drive circuits of substrate processing systems
Granted: March 25, 2025
Patent Number:
12261029
A direct drive system for providing RF power to a component of a substrate processing system includes a direct drive circuit including a switch and configured to supply RF power to the component. A switch protection module is configured to monitor a load current and a load voltage in a processing chamber, calculate load resistance based on the load current and the load voltage, compare the load resistance to a first predetermined load resistance, and adjust at least one of an RF power…
Plenum assemblies for cooling transformer coupled plasma windows
Granted: March 25, 2025
Patent Number:
12261018
A plenum for a dielectric window of a substrate processing system includes a first inlet port, a second inlet port, and a body. The body includes: a first recessed area configured to hold a first coil; a second recessed area configured to hold a second coil; a third recessed area configured to oppose a first area of the dielectric window, receive a first coolant from the first inlet port, and direct the first coolant across the first area to cool a first portion of the dielectric window;…
In-situ PECVD cap layer
Granted: March 18, 2025
Patent Number:
12252782
Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as…
