Non-Binary Layered Low Density Parity Check Decoder
Granted: April 2, 2015
Application Number:
20150092290
A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.
Systems and Methods for Enhanced Data Recovery in a Solid State Memory System
Granted: March 26, 2015
Application Number:
20150089330
Systems and method relating generally to data processing, and more particularly to systems and methods for recovering data from a solid state memory.
DYNAMIC STORAGE VOLUME CONFIGURATION BASED ON INPUT/OUTPUT REQUESTS
Granted: March 26, 2015
Application Number:
20150089132
A storage system includes a plurality hard disk drives and a plurality of solid-state drives and a storage controller operable to manage the hard disk drives and solid-state drives as a plurality of logical volumes, and categorize input/output requests to the logical volumes into types based on sizes of the input/output requests (e.g., smaller and larger). The storage controller is also operable to reconfigure the logical volumes from the hard disk drives and the solid-state drives based…
SOLID STATE DRIVES THAT CACHE BOOT DATA
Granted: March 26, 2015
Application Number:
20150089102
Methods and structure for utilizing a Solid State Drive (SSD) to enhance boot time for a computer. The computer includes an SSD that stores a boot cache for an Operating System of a computer, a Hard Disk Drive that stores the Operating System, and a processor. The processor is able to load an interrupt handler that intercepts Input/Output requests directed to the Hard Disk Drive prior to loading a kernel of the Operating System. The interrupt handler is able to determine whether each…
Method Of Calibrating a Slicer In a Receiver Or the Like
Granted: March 26, 2015
Application Number:
20150085957
A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps…
Bit-Line Discharge Assistance in Memory Devices
Granted: March 26, 2015
Application Number:
20150085592
One embodiment is an apparatus that has a memory array, a discharge device, and a discharge assistance controller. The memory array has memory cells arranged in at least one column that is coupled to a read bit line, and the discharge device is configured to provide discharge assistance to the read bit line. The discharge assistance controller is configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line.
PING-PONG BUFFER USING SINGLE-PORT MEMORY
Granted: March 26, 2015
Application Number:
20150085587
A method of controlling a ping-pong buffer includes selectively providing one of a ping gated write clock signal and a ping gated read clock signal to a single-port ping buffer, and selectively providing a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A controller of a ping-pong buffer includes a ping multiplexer and a pong multiplexer. The ping multiplexer selectively provides a ping gated write clock signal or a ping gated read clock…
System and Method for Monitoring Preamble Signal Quality
Granted: March 26, 2015
Application Number:
20150085392
The disclosure is directed to a system and method of determining signal quality based upon at least one of: a comparison of energy content of the signal to a threshold energy content, a comparison of energy content of the fundamental harmonic of the signal to a specified percentage of the energy content of the signal, and a comparison of a difference between phase of the signal and a target phase to a threshold phase difference.
METHOD OF ERASE STATE HANDLING IN FLASH CHANNEL TRACKING
Granted: March 19, 2015
Application Number:
20150082121
An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.
SPATIALLY DECOUPLED REDUNDANCY SCHEMES FOR A SOLID STATE DRIVE (SSD)
Granted: March 19, 2015
Application Number:
20150082124
An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to write user data using a redundancy scheme. Information about the redundancy is (i) stored in a location separate from the data and (ii) used to recover potentially corrupted user data.
Systems and Methods for Fragmented Data Recovery
Granted: March 19, 2015
Application Number:
20150082115
Systems and method relating generally to data processing, and more particularly to systems and methods for fragmenting a data set and recovering the fragmented data set.
IN-LINE DEDUPLICATION FOR A NETWORK AND/OR STORAGE PLATFORM
Granted: March 19, 2015
Application Number:
20150081649
An apparatus comprising a classification block, a pattern generator block, a hash key block and a replacement block. The classification block may be configured to (i) receive a data signal and (ii) identify a portion of the data signal that contains a duplicated data pattern. The pattern generation block may be configured to generate a common continuous pattern of data in response to the data signal. The hash key block may be configured to generate a hash key representing the duplicated…
Systems and Methods for Recovered Data Stitching
Granted: March 19, 2015
Application Number:
20150081626
Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set.
SENSING TECHNIQUE FOR SINGLE-ENDED BIT LINE MEMORY ARCHITECTURES
Granted: March 19, 2015
Application Number:
20150078103
A sense amplifier includes a latch, first and second switching circuitry, and control circuitry. The first switching circuitry selectively couples a voltage supply node and/or a voltage return node of the latch to a voltage supply and/or a voltage return of the sense amplifier, respectively, as a function of a first control signal. The second switching circuitry couples a first sensing node in the sense amplifier with a first bit line of a first sub-bank in one of multiple memory banks…
REDUCED POLAR CODES
Granted: March 19, 2015
Application Number:
20150077277
A method for encoding a reduced polar code is disclosed. The method generally includes steps (A) to (C). Step (A) may generate the intermediate codeword by polar code encoding input data. Step (B) may remove one or more bits from one of (i) a first part of the intermediate codeword and (ii) a second part of the intermediate codeword. Step (C) may generate an output codeword by concatenating the first part of the intermediate codeword with the second part of the intermediate codeword…
EFFICIENT CACHING OF FILE SYSTEM JOURNALS
Granted: March 12, 2015
Application Number:
20150074355
An apparatus includes a memory and a controller. The memory may be configured to implement a cache and store meta-data. The cache generally comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines is associated with meta-data indicating one or more of a dirty state, an invalid state, and a partially dirty state. The controller is connected to the memory and may be…
DYNAMIC MAP PRE-FETCHING FOR IMPROVED SEQUENTIAL READS OF A SOLID-STATE MEDIA
Granted: March 12, 2015
Application Number:
20150074328
Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request…
Active Recycling for Solid State Drive
Granted: March 12, 2015
Application Number:
20150074327
A solid state drive and a method for providing active recycling for the solid state drive are disclosed. The solid state drive includes a plurality of blocks and each of the plurality of blocks includes a plurality of pages. The method steps include receiving a read request from a data requester; identifying at least one page containing data requested by the read request; determining whether the at least one page belongs to a block identified for active recycling; writing the at least…
Array-Reader Based Magnetic Recording Systems With Mixed Synchronization
Granted: March 12, 2015
Application Number:
20150070796
A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number…
Systems and Methods for Multi-Level Encoding and Decoding
Granted: March 5, 2015
Application Number:
20150062734
A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate…
