Systems and Methods for Multiple Sensor Noise Predictive Filtering
Granted: March 5, 2015
Application Number:
20150067685
The present invention is related to systems and methods for branch metric calculation based on multiple data streams in a data processing circuit.
INPUT/OUTPUT REQUEST SHIPPING IN A STORAGE SYSTEM WITH MULTIPLE STORAGE CONTROLLERS
Granted: March 5, 2015
Application Number:
20150067253
Systems and methods presented herein provide for input/output shipping between storage controllers in a storage system. One storage system comprises a plurality of logical volumes, a host driver operable to process input/output requests to the logical volumes, and a plurality of storage controllers coupled between the server and the logical volumes. A first of storage controllers is operable to receive an input/output request from the host driver for one of the logical volumes, and…
MAPPING BETWEEN VARIABLE WIDTH SAMPLES AND A FRAME
Granted: March 5, 2015
Application Number:
20150063217
An apparatus having a plurality of first circuits, a second circuit and a plurality of processor circuits is disclosed. Each first circuit is configured to store a plurality of samples corresponding to a plurality of channels. At least two of the samples having different widths. The second circuit is configured to store a plurality of frames each sized to contain two or more of the samples. The processor circuits are configured to (i) read the samples from the first circuits…
Systems and Methods for Variable Sector Count Spreading and De-Spreading
Granted: March 5, 2015
Application Number:
20150062738
Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.
Adaptive Pattern Detection for Pattern-Dependent Write Current Control in a Magnetic Recording System
Granted: March 5, 2015
Application Number:
20150062737
The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The…
Systems and Methods for Multi-Level Encoding and Decoding
Granted: March 5, 2015
Application Number:
20150062734
A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate…
Systems and Methods for Two Stage Tone Reduction
Granted: March 5, 2015
Application Number:
20150062732
Systems and method relating generally to data processing, and more particularly to systems and methods for tone reduction in relation to data transmission.
Array-Reader Based Magnetic Recording Systems With Quadrature Amplitude Modulation
Granted: March 5, 2015
Application Number:
20150062730
A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a quadrature amplitude modulator operable to combine the analog signals to yield a quadrature amplitude modulated signal, a quadrature amplitude demodulator operable to yield a plurality of demodulated signals from the quadrature amplitude modulated signal corresponding to each channel of the array, and a joint equalizer operable to filter the…
Performance Improvements in Input / Output Operations Between a Host System and an Adapter-Coupled Cache
Granted: February 26, 2015
Application Number:
20150058557
A modified or host driver operable on a host computer communicates with a host interface of a PCIe adapter. A controller memory space is managed by the kernel space of the host operating system. The modified driver entirely avoids the overhead associated with making a copy from the application or user space to a separate kernel space managed by the operating system in the host computer. The modified driver uses a base address register to identify the location of the cache storage in the…
Systems and Methods for Enhanced Data Encoding and Decoding
Granted: February 26, 2015
Application Number:
20150058693
Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.
DATA STORAGE CONTROLLER AND METHOD FOR EXPOSING INFORMATION STORED IN A DATA STORAGE CONTROLLER TO A HOST SYSTEM
Granted: February 26, 2015
Application Number:
20150058533
A data storage controller exposes information stored in a locally managed volatile memory store to a host system. The locally managed volatile memory store is mapped to a corresponding portion of a peripheral component interconnect express (PCIe) compliant memory space managed by the host system. Backup logic in the data storage controller responds to a power event detected at the interface between the data storage controller and the host system by copying the contents of the volatile…
ECHO CANCELLATION WITH QUANTIZATION COMPENSATION
Granted: February 26, 2015
Application Number:
20150055774
An apparatus having a first circuit and a second circuit is disclosed. The first circuit is configured to generate a first intermediate signal by expanding a first input signal subjected to a quantization. The second circuit is configured to generate a second intermediate signal based on a second input signal. The second intermediate signal approximates an echo in the first input signal caused by the second input signal. The second circuit is also configured to generate a third…
PRECISE TIMESTAMPING OF ETHERNET PACKETS BY COMPENSATING FOR START-OF-FRAME DELIMITER DETECTION DELAY AND DELAY VARIATIONS
Granted: February 26, 2015
Application Number:
20150055644
An apparatus includes a synchronization block and a physical coding sublayer block. The synchronization block may be configured to determine a position of a start of frame delimiter. The physical coding sublayer block may be configured to measure a delay through the physical coding sublayer block and provide delay and delay variation compensation based upon the measured delay.
Systems and Methods for Multi-Resolution Data Sensing
Granted: February 26, 2015
Application Number:
20150055249
Systems and methods relating generally to sensing information, and more particularly to systems and methods for utilizing multiple readers to sense information.
SYSTEM AND METHOD FOR PROVIDING AN ELECTRON BLOCKING LAYER WITH DOPING CONTROL
Granted: February 19, 2015
Application Number:
20150048310
Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.
PREDICTIVE FAILURE ANALYSIS TO TRIGGER REBUILD OF A DRIVE IN A RAID ARRAY
Granted: February 12, 2015
Application Number:
20150046756
An apparatus comprising a first interface, a second interface and a processor. The first interface may be configured to connect to a host device. The second interface may be configured to connect to a plurality of drives. The processor may be configured to (i) periodically read a drive attribute from each of the drives, (ii) determine a risk factor based on the attribute, (iii) determine if each of the drives is likely to fail based on the risk factor, (iv) determine a cost factor for…
DEPTH IMAGE COMPRESSION AND DECOMPRESSION UTILIZING DEPTH AND AMPLITUDE DATA
Granted: February 12, 2015
Application Number:
20150043807
In one embodiment, an image processing system comprises an image processor configured to obtain depth and amplitude data associated with a depth image, to identify a region of interest based on the depth and amplitude data, to separately compress the depth and amplitude data based on the identified region of interest to form respective compressed depth and amplitude portions, and to combine the separately compressed portions to provide a compressed depth image. The image processor may…
MEMORY CELL HAVING BUILT-IN WRITE ASSIST
Granted: February 12, 2015
Application Number:
20150043270
A memory cell includes a storage element including a pair of cross-coupled inverters, and first switching circuitry for selectively connecting at least one internal storage node of the storage element with a corresponding bit line as a function of a first control signal. Write assist circuitry is connected between a supply node of a device of at least one of the cross-coupled inverters and a voltage supply of the memory cell, and second switching circuitry selectively couples the supply…
OBJECT RECOGNITION AND TRACKING USING A CLASSIFIER COMPRISING CASCADED STAGES OF MULTIPLE DECISION TREES
Granted: February 5, 2015
Application Number:
20150036942
An image processor comprises first and second hardware accelerators and is configured to implement a classifier. The classifier in some embodiments comprises a cascaded classifier having a plurality of stages with each such stage implementing a plurality of decision trees. At least one of the first and second hardware accelerators of the image processor is configured to generate an integral image based on a given input image, and the second hardware accelerator is configured to process…
ACQUIRING RESOURCES FROM LOW PRIORITY CONNECTION REQUESTS IN SAS
Granted: February 5, 2015
Application Number:
20150039796
Systems and methods herein provide for managing connection requests through a Serial Attached Small Computer System Interface (SAS) expander. In one embodiment, the expander receives a low priority open address frame (OAF) that includes a source address and a destination address. The expander also receives a high priority OAF that includes a source address and a destination address. The high priority OAF requires at least a portion of a partial path acquired by the low priority OAF for…
