Tracking and Utilizing Second Level Map Index for Recycling of Solid State Drive Blocks
Granted: April 30, 2015
Application Number:
20150120989
A recycling method for a solid state drive is disclosed. The method includes selecting a logical block for recycle wherein the logical block includes a plurality of pages across a plurality of flash dies. The method also includes retrieving an address map index record associated with the logical block selected for recycle. For each particular address map index stored in the address map index record, the recycling method retrieves a set of address map entries referenced by the particular…
Data Interface for Point-to-Point Communications Between Devices
Granted: April 30, 2015
Application Number:
20150120981
A data interface is provided for point-to-point communications between two devices, such as a read channel and a disk controller in an HDD system. An interface for communications from a transmitting device to a receiving device comprises a data bus configured to communicate m bits of data and a corresponding n bit data tag, wherein a given n bit data tag identifies a data type of a corresponding m bits of data on the data bus. An acknowledge signal from the receiving device optionally…
METHOD AND SYSTEM FOR SESSION BASED DATA MONITORING FOR WIRELESS EDGE CONTENT CACHING NETWORKS
Granted: April 30, 2015
Application Number:
20150117226
Aspects of the disclosure pertain to methods and systems that are configured to monitor data usage at a network edge. In an implementation, a method includes monitoring data usage information associated with a mobile user session between a mobile device and a plurality of edges nodes of a communication network, where the plurality of edge nodes includes at least a beginning edge node and a final edge node. The method also includes storing data usage information from the monitored data…
Systems and Methods for Sub-Zero Threshold Characterization in a Memory Cell
Granted: April 30, 2015
Application Number:
20150117097
Systems and method relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory.
Transmitter Training Using Receiver Equalizer Coefficients
Granted: April 23, 2015
Application Number:
20150110165
A method of adjusting a post-cursor tap weight in a transmitter FIR filter in a high-speed digital data transmission system. A receiver, over a forward channel, receives a signal from the transmitter and equalizes the received signal using an adaptive analog equalizer coupled to the forward channel and a decision feedback equalizer (DFE) coupled to the analog equalizer. A gain coefficient used to adjust the peaking by the analog equalizer is adapted using an error signal generated by the…
GENERATING SOFT DECODING INFORMATION FOR FLASH MEMORY ERROR CORRECTION USING HARD DECISION PATTERNS
Granted: April 23, 2015
Application Number:
20150113354
A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region…
SENDING FAILURE INFORMATION FROM A SOLID STATE DRIVE (SSD) TO A HOST DEVICE
Granted: April 23, 2015
Application Number:
20150113335
A system, method, and computer program product are provided for a host device to request and obtain failure information from a solid state drive (SSD). In operation, an error is detected during an operation associated with a solid state drive. Additionally, a command to return failure information is provided to the solid state drive by a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure…
Systems and Methods for Soft Data Utilization in a Solid State Memory System
Granted: April 23, 2015
Application Number:
20150113318
Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.
SYSTEM AND METHOD FOR DETECTING SERVER REMOVAL FROM A CLUSTER TO ENABLE FAST FAILOVER OF STORAGE
Granted: April 23, 2015
Application Number:
20150113312
Aspects of the disclosure pertain to a system and method for detecting server removal from a cluster to enable fast failover of storage (e.g., logical volumes). A method of operation of a storage controller of a cluster is disclosed. The method includes receiving a signal. The method further includes, based upon the received signal, determining that communicative connection between a second storage controller of the cluster and the first storage controller of cluster is unable to be…
Systems and Methods for Latency Based Data Recycling in a Solid State Memory System
Granted: April 23, 2015
Application Number:
20150113205
Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory.
CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS
Granted: April 23, 2015
Application Number:
20150109052
In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a…
Systems and Methods for Multi-Algorithm Concatenation Encoding and Decoding
Granted: April 16, 2015
Application Number:
20150106675
Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.
Speculative Bit Error Rate Calculator
Granted: April 16, 2015
Application Number:
20150106666
An apparatus for calculating a speculative bit error rate includes a data decoder operable to iteratively decode received data to yield decoded data, and a speculative bit error calculator operable to calculate a bit error rate based on the decoded data and the received data while the data decoder is decoding the received data. The bit error rate is updated with each decoding iteration in the data decoder.
DE-INTERLEAVING ON AN AS-NEEDED BASIS
Granted: April 16, 2015
Application Number:
20150106577
One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The…
DIGITAL FREQUENCY BAND DETECTOR FOR CLOCK AND DATA RECOVERY
Granted: April 16, 2015
Application Number:
20150103961
A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each…
MEMORY ARRAY ARCHITECTURES HAVING MEMORY CELLS WITH SHARED WRITE ASSIST CIRCUITRY
Granted: April 16, 2015
Application Number:
20150103604
A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration. The first inverter is connected between the first virtual power supply node and the second power supply node, and the second inverter is connected between the second virtual power…
ADAPTIVE POWER-DOWN OF DISK DRIVES BASED ON PREDICTED IDLE TIME
Granted: April 9, 2015
Application Number:
20150100810
Systems and methods presented herein provide a storage system that adaptively powers-down one or more disk drives based on the predicted idle time of each disk drive. One embodiment includes a storage controller that includes a processor operable to track idle durations of the disk drive. When an idle duration ends, the processor associates the idle duration with a time window that includes that idle duration. Each time window is associated with a number of previous idle durations of the…
VOLTAGE FOLLOWER HAVING A FEED-FORWARD DEVICE
Granted: April 9, 2015
Application Number:
20150097611
A circuit is described that includes a voltage follower device and a feed-forward device. In an implementation, the circuit includes a voltage follower device that includes an input and an output. The voltage follower device is configured to transfer a voltage signal at least substantially unchanged from the input to the output of the voltage follower device. The circuit also includes a feed-forward device that includes an input and an output. The input of the feed-forward device is…
REDUCING CURRENT VARIATION WHEN SWITCHING CLOCKS
Granted: April 2, 2015
Application Number:
20150091620
An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal.
FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POINTS OF CELL VOLTAGE DISTRIBUTIONS USING HISTOGRAMS
Granted: April 2, 2015
Application Number:
20150092489
Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple…
