ARBITRATION SUSPENSION IN A SAS DOMAIN
Granted: February 5, 2015
Application Number:
20150039932
Systems and methods presented herein provide for managing connections in a SAS domain comprising at least first and second expanders. The first expander detects a failure of the initiator and indicates a change in the SAS domain to the second expander. The second expander detects an increase in arbitration wait time for a connection between the initiator and the target device, determines a race condition exists in the second expander, denies the connection between the initiator and the…
System and Method of Hinted Cache Data Removal
Granted: February 5, 2015
Application Number:
20150039835
The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver, a priority controller, and a data scrubber. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data transfer request includes a request to…
System and Method of Caching Hinted Data
Granted: February 5, 2015
Application Number:
20150039832
The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver and a priority controller. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data packets are associated with at least a first (high) priority…
ACQUIRING RESOURCES FROM LOW PRIORITY CONNECTION REQUESTS IN SAS
Granted: February 5, 2015
Application Number:
20150039796
Systems and methods herein provide for managing connection requests through a Serial Attached Small Computer System Interface (SAS) expander. In one embodiment, the expander receives a low priority open address frame (OAF) that includes a source address and a destination address. The expander also receives a high priority OAF that includes a source address and a destination address. The high priority OAF requires at least a portion of a partial path acquired by the low priority OAF for…
MULTI-PROTOCOL STORAGE CONTROLLER
Granted: February 5, 2015
Application Number:
20150039787
Systems and methods presented herein provide for coupling a storage controller to a plurality of different storage device types. One embodiment of the storage controller includes an interface operable to communicatively couple to a storage device. The storage controller also includes a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, and to detect a protocol of the storage device when the storage…
Switch Device With Device-Specified Bridge Domains
Granted: January 29, 2015
Application Number:
20150030027
A switch includes registers, a parser and port selection logic. The registers store an address in multiple locations. The address defines a bridge domain. Each bridge domain defines a set of switch ports. The parser identifies when a received frame includes a virtual local area network (VLAN) identifier. The parser uses the VLAN identifier to locate the address in the registers. The port selection logic is responsive to one of a first index from a first table that includes port…
DEADLOCK DETECTION AND RECOVERY IN SAS
Granted: January 29, 2015
Application Number:
20150033074
Systems and methods herein provide for managing devices through a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes a processor adapted to detect deadlock conditions in a SAS environment. In one embodiment, the SAS expander is operable to detect an Open Address Frame associated with a connection request from a source device to a destination device. The Open Address Frame includes a source address and a destination address associated with the source…
SOLID STATE DRIVE EMERGENCY PRE-BOOT APPLICATION PROVIDING EXPANDED DATA RECOVERY FUNCTION
Granted: January 29, 2015
Application Number:
20150033065
An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a user area and a non-user area. The user area is generally enabled to store and retrieve data in a logical block address space of a host. The non-user area stores a failure-specific recovery routine. The controller may be communicatively coupled to the non-volatile memory. The controller is generally enabled, when operationally coupled to the host, (i) to respond to host commands to read and…
DYNAMIC SELECTION OF CACHE LEVELS
Granted: January 29, 2015
Application Number:
20150032963
An apparatus having a first circuit and a second circuit is disclosed. The first circuit is configured to generate an access request having a first address. The second circuit is configured to (i) initiate a change in a load value of a cache system in response to the access request. The cache system has a plurality of levels. The load value represents a work load on the cache system. The second circuit is further configured to (ii) generate a second address from the first address in…
IMAGE PROCESSOR CONFIGURED FOR EFFICIENT ESTIMATION AND ELIMINATION OF BACKGROUND INFORMATION IN IMAGES
Granted: January 29, 2015
Application Number:
20150030232
An image processing system comprises an image processor implemented using at least one processing device and adapted for coupling to an image source, such as a depth imager. The image processor is configured to compute a convergence matrix and a noise threshold matrix, to estimate background information of an image utilizing the convergence matrix, and to eliminate at least a portion of the background information from the image utilizing the noise threshold matrix. The background…
Array-Reader Based Magnetic Recording Systems With Frequency Division Multiplexing
Granted: January 29, 2015
Application Number:
20150029608
A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a modulator operable to combine the analog signals to yield a frequency division multiplexed signal, a demodulator operable to yield a plurality of demodulated signals from the frequency division multiplexed signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an…
Data Decoder With Trapping Set Flip Bit Mapper
Granted: January 22, 2015
Application Number:
20150026536
A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate…
CACHE SYSTEM FOR MANAGING VARIOUS CACHE LINE CONDITIONS
Granted: January 22, 2015
Application Number:
20150026411
A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a…
SELF-ADJUSTING CACHING SYSTEM
Granted: January 22, 2015
Application Number:
20150026403
An apparatus having a cache and a controller is disclosed. The controller is configured to (i) gather a plurality of statistics corresponding to a plurality of requests made from one or more hosts to access a memory during an interval, (ii) store data of the requests selectively in the cache in response to a plurality of headers and (iii) adjust one or more parameters in the headers in response to the statistics. The requests and the parameters are recorded in the headers.
GESTURE RECOGNITION METHOD AND APPARATUS BASED ON ANALYSIS OF MULTIPLE CANDIDATE BOUNDARIES
Granted: January 22, 2015
Application Number:
20150023607
An image processing system comprises an image processor configured to identify a plurality of candidate boundaries in an image, to obtain corresponding modified images for respective ones of the candidate boundaries, to apply a mapping function to each of the modified images to generate a corresponding vector, to determine sets of estimates for respective ones of the vectors relative to designated class parameters, and to select a particular one of the candidate boundaries based on the…
Orientation-Based Camera Operation
Granted: January 22, 2015
Application Number:
20150022704
An electronic device comprising an image sensor, an orientation sensor, and a user interface, may be operable to capture photographs via the image sensor. Input to the user interface required for triggering a photo capture may depend on an orientation of the electronic device indicated by the orientation sensor. Input required to trigger a photo capture while the orientation sensor indicates a first orientation of the electronic device may be different than input required to trigger a…
FEEDBACK/FEED FORWARD SWITCHED CAPACITOR VOLTAGE REGULATION
Granted: January 22, 2015
Application Number:
20150022169
A method of controlling a switched capacitor voltage regulator includes modifying a topology factor associated with the switched capacitor voltage regulator in response to a change in output voltage associated with the switched capacitor voltage regulator, thereby maintaining an average output voltage associated with the switched capacitor voltage regulator. The method also includes modifying a loop delay associated with the switched capacitor voltage regulator in response to a change in…
Storage Media Inter-Track interference Cancellation
Granted: January 15, 2015
Application Number:
20150015984
Described embodiments provide a method of cancelling inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A read channel reads sectors in a desired track of the storage medium. A decoder of the read channel decodes the read sectors, and if the read sectors are incorrectly recovered from the storage medium, selected sectors of a first adjacent track and a second adjacent track are read. An ITI canceller of the read channel estimates ITI in…
MEMORY SYSTEM FOR SHADOWING VOLATILE DATA
Granted: January 15, 2015
Application Number:
20150019795
An apparatus configured to shadow volatile data while minimizing read latency is described. In an implementation, the apparatus includes a memory controller configured to operatively couple to a volatile memory device and a non-volatile memory device. The volatile memory device includes a volatile memory cell and the non-volatile memory device includes a corresponding non-volatile memory cell. The volatile memory device has a first transfer speed and the non-volatile memory device has a…
Prioritized Spin-Up of Drives
Granted: January 15, 2015
Application Number:
20150015987
A data storage system controller designates critical drives for staggered spin up and other, non-critical drives for spin up only when the controller notifies the appropriate expander. Each expander in the data storage system maintains configuration information for each PHY of the expander and reports completion of spin up when all of the drives designated “staggered spin up” have been spun up. Alternatively, an expander maintains PHY configuration data, designating each PHY as…
