CLOCK AND DATA RECOVERY ARCHITECTURE WITH ADAPTIVE DIGITAL PHASE SKEW
Granted: January 15, 2015
Application Number:
20150016497
In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation…
Prioritized Spin-Up of Drives
Granted: January 15, 2015
Application Number:
20150015987
A data storage system controller designates critical drives for staggered spin up and other, non-critical drives for spin up only when the controller notifies the appropriate expander. Each expander in the data storage system maintains configuration information for each PHY of the expander and reports completion of spin up when all of the drives designated “staggered spin up” have been spun up. Alternatively, an expander maintains PHY configuration data, designating each PHY as…
Storage Media Inter-Track interference Cancellation
Granted: January 15, 2015
Application Number:
20150015984
Described embodiments provide a method of cancelling inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A read channel reads sectors in a desired track of the storage medium. A decoder of the read channel decodes the read sectors, and if the read sectors are incorrectly recovered from the storage medium, selected sectors of a first adjacent track and a second adjacent track are read. An ITI canceller of the read channel estimates ITI in…
RADIO FREQUENCY COMPOSITE CLASS-S POWER AMPLIFIER HAVING DISCRETE POWER CONTROL
Granted: January 15, 2015
Application Number:
20150015329
A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The…
Systems and Methods for Correlation Based Data Alignment
Granted: January 8, 2015
Application Number:
20150012800
A data processing system is disclosed including a data detector, a data decoder and an alignment detector. The data detector is operable to apply a data detection algorithm to generate detected values for a data sector. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The alignment detector is operable to calculate an offset between multiple versions of the data sector by correlating the multiple…
REDUNDANT ARRAY OF INDEPENDENT DISKS VOLUME CREATION
Granted: January 8, 2015
Application Number:
20150012702
Methods and structure for automatic creation of Redundant Array of Independent Disks (RAID) volumes are provided. The system comprises A RAID controller that includes a memory and a processor. The memory stores information describing storage devices of a storage system. The processor is able to receive a request to generate a RAID volume, to access the memory to identify a first group of storage devices that each have a first storage capacity, and to determine an expected size of a…
DYNAMIC START-UP CIRCUIT FOR HYSTERETIC LOOP SWITCHED-CAPACITOR VOLTAGE REGULATOR
Granted: January 8, 2015
Application Number:
20150008894
A startup circuit for use with a SCVR circuit includes a comparator operative to generate a first control signal as a function of a comparison between an output voltage generated by the SCVR circuit and a reference voltage, the first control signal being used to disable the startup circuit. The startup circuit further includes a reference generator and a controller. The reference generator is coupled with the comparator and operative to generate at least first, second and third voltages,…
BACKUP OF CACHED DIRTY DATA DURING POWER OUTAGES
Granted: January 1, 2015
Application Number:
20150006815
Systems and methods presented herein provide for backing up cached dirty data during power outages. In one embodiment, a system includes a controller operable to process input/output requests from a host system, and a cache memory operable to cache dirty data pertaining to the input/output requests. The system also includes a nonvolatile memory operable to back up the dirty data during a power outage. The controller comprises a hardware register operable to map directly to the cache…
USER INTERFACE COMPRISING RADIAL LAYOUT SOFT KEYPAD
Granted: December 25, 2014
Application Number:
20140380223
A processing device is configured to provide a user interface comprising a radial layout soft keypad. The radial layout soft keypad comprises a central region and one or more concentric groupings of keys arranged around the central region. For example, the one or more concentric groupings of keys may be arranged as multiple concentric circular rows of keys substantially surrounding the central region, with all of the keys of the concentric circular rows being simultaneously visible in…
Systems and Methods for Data Processing Control
Granted: December 18, 2014
Application Number:
20140372836
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data encoding.
SYSTEM AND METHOD FOR PROVIDING IMPROVED SYSTEM PERFORMANCE BY MOVING PINNED DATA TO OPEN NAND FLASH INTERFACE WORKING GROUP MODULES WHILE THE SYSTEM IS IN A RUNNING STATE
Granted: December 18, 2014
Application Number:
20140372672
Aspects of the disclosure pertain to a system and method for providing improved system performance by moving pinned data to ONFI module(s) while the system is in a running state. Further, when a virtual array of the system is offline, the system allows for scheduling and performance of background operations on virtual arrays which are still online. These characteristics promote the ability of the online virtual arrays to operate efficiently in the presence of the pinned data.
METHOD AND APPARATUS FOR INCREASING FRAME RATE OF AN IMAGE STREAM USING AT LEAST ONE HIGHER FRAME RATE IMAGE STREAM
Granted: December 11, 2014
Application Number:
20140362289
An image processing system comprises an image processor configured to obtain a first image stream having a first frame rate and a second image stream having a second frame rate lower than the first frame rate, to recover additional frames for the second image stream based on existing frames of the first and second image streams, and to utilize the additional frames to provide an increased frame rate for the second image stream. Recovering additional frames for the second image stream…
APPARATUS FOR PROCESSING SIGNALS CARRYING MODULATION-ENCODED PARITY BITS
Granted: December 4, 2014
Application Number:
20140359394
A receiver configured for use in a communication system, such as a magnetic recording channel, and having a soft-output channel detector provided with a soft-input/soft-output (SISO) modulation codec for parity bits of a block error-correction code. A transmitter of the communication system is configured to encode data by applying a modulation code to the parity bits that have been generated using the block error-correction code. The SISO modulation codec provides an interface between…
OPTIMIZING BOOT TIME OF A STORAGE SYSTEM
Granted: December 4, 2014
Application Number:
20140359266
Systems and methods herein provide a storage system that optimizes the boot time when the storage system is rebooted. One embodiment includes a storage controller operable to determine a topology of one or more storage devices. The storage controller stores the topology in memory. When the storage controller detects a system reboot event, it provides the stored topology to the host and directs the host to reboot with the stored topology.
CONFIRMED DIVERT BITMAP TO SYNCHRONIZE RAID FIRMWARE OPERATIONS WITH FAST-PATH HARDWARE I/O PROCESSING
Granted: December 4, 2014
Application Number:
20140359216
A storage controller system is provided for the monitoring of fast path processing of I/Os to a storage device where the storage controller system allows for processing of I/Os to be monitored through the use of counters in a storage controller based upon the type of I/O issued to the storage controller as well as the conditions associated with the I/O, while providing a bitmap and associated divert bits and counters to monitor the processing of the I/Os in the storage controller.…
Shift Register-Based Layered Low Density Parity Check Decoder
Granted: November 27, 2014
Application Number:
20140351671
An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate…
VARIABLE REDUNDANCY IN A SOLID STATE DRIVE
Granted: November 27, 2014
Application Number:
20140351486
An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to provide a first redundancy scheme when user data occupies less than a preconfigured limit and a second redundancy scheme that protects less than all of the user data when the user data occupies greater than the…
MOISTURE BARRIER FOR A WIRE BOND
Granted: November 27, 2014
Application Number:
20140349475
An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface
SEMICONDUCTOR OPTICAL EMITTING DEVICE WITH LENS STRUCTURE FORMED IN A CAVITY OF A SUBSTRATE OF THE DEVICE
Granted: November 27, 2014
Application Number:
20140348197
A semiconductor optical emitting device comprises an at least partially transparent substrate, an active semiconductor structure arranged on a first side of the substrate, and a lens structure formed at least partially within a cavity on a second side of the substrate. Light generated by the active semiconductor structure is emitted through the substrate and the lens structure. The cavity may comprise a bottom surface and a plurality of sidewalls, with the plurality of sidewalls…
LANE-BASED MULTIPLEXING FOR PHYSICAL LINKS IN SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE ARCHITECTURES
Granted: November 20, 2014
Application Number:
20140341231
Methods and structure for lane-based multiplexing of physical links are provided. In one embodiment, a Serial Attached Small Computer System Interface (SAS) device is provided. The SAS device comprises a physical link and a controller. The controller is able to time division multiplex the physical link into multiple lanes, and to manage a first connection along one or more of the lanes of the physical link. The controller is further able to detect a request for a second connection, to…
