Method and System for Sliding-Window Based Phase, Gain, Frequency and DC Offset Estimation for Servo Channel
Granted: November 20, 2014
Application Number:
20140340780
Sliding-window based data processing includes receiving an analog signal, converting the analog signal to a series of digital samples synchronous to a sampling clock, performing a first discrete Fourier transform on a first portion of the series of digital samples, performing a second discrete Fourier transform on a second portion of the series of digital samples, performing a third discrete Fourier transform on a third portion of the series of digital samples, generating a first series…
LANE-BASED MULTIPLEXING FOR PHYSICAL LINKS IN SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE ARCHITECTURES
Granted: November 20, 2014
Application Number:
20140341231
Methods and structure for lane-based multiplexing of physical links are provided. In one embodiment, a Serial Attached Small Computer System Interface (SAS) device is provided. The SAS device comprises a physical link and a controller. The controller is able to time division multiplex the physical link into multiple lanes, and to manage a first connection along one or more of the lanes of the physical link. The controller is further able to detect a request for a second connection, to…
METHODS AND SYSTEMS FOR REDUCING SPURIOUS INTERRUPTS IN A DATA STORAGE SYSTEM
Granted: November 20, 2014
Application Number:
20140344492
A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt…
TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES
Granted: November 20, 2014
Application Number:
20140344616
A storage subsystem receives writes via a storage subsystem interface and reduces a number of the writes. Data associated with the reduced number of writes is stored in storage devices of a single drive. Computed redundancy information is stored in the storage devices. A data redundancy scheme is implemented via a disk controller that is enabled to operate without a loss of data in the presence of at least a single failure of any of the storage devices.
Systems and Methods for Processing Data With Microcontroller Based Retry Features
Granted: November 13, 2014
Application Number:
20140337676
A data processing system is disclosed including a data detector, a data decoder and a microcontroller. The data detector is operable to apply a data detection algorithm to generate detected values for data sectors. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The microcontroller is operable to configure the data detector and the data decoder to apply the data detection algorithm and the data…
INTELLIGENT CACHE WINDOW MANAGEMENT FOR STORAGE SYSTEMS
Granted: November 13, 2014
Application Number:
20140337583
Methods and structure for intelligent cache window management are provided. The system comprises a memory and a cache manager. The memory stores entries of cache data for a logical volume. The cache manager is able to track usage of the logical volume by a host, and to identify logical block addresses of the logical volume to cache based on the tracked usage. The cache manager is further able to determine that one or more write operations are directed to the identified logical block…
METHOD AND SYSTEM FOR I/O FLOW MANAGEMENT FOR PCIe DEVICES
Granted: November 13, 2014
Application Number:
20140337540
Disclosed is a system and method for generating IO in PCIe devices and flow management of the IO.
PREDICTION BASED METHODS FOR FAST ROUTING OF IP FLOWS USING COMMUNICATION/NETWORK PROCESSORS
Granted: November 13, 2014
Application Number:
20140334491
Aspects of the disclosure pertain to a system and method for providing prediction based, fast routing of IP flows. A hash table-based mechanism is implemented by the system such that classification information obtained and/or utilized for a first packet of an IP flow is applied to subsequent packets of the IP flow, thereby promoting packet processing efficiency for the flow.
Systems and Methods for Data Processor Marginalization Based Upon Bit Error Rate
Granted: November 13, 2014
Application Number:
20140334281
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability, and/or operational improvement capability.
Systems and Methods for Energy Based Head Contact Detection
Granted: November 13, 2014
Application Number:
20140334278
The present inventions are related to systems and methods for determining contact between two elements, and more particularly to systems and methods for determining contact between a head assembly and a storage medium.
Systems and Methods for Characterizing Head Contact
Granted: November 13, 2014
Application Number:
20140334280
The present inventions are related to systems and methods for determining contact between two elements, and more particularly to systems and methods for determining contact between a head assembly and a storage medium.
Systems and Methods for Detecting Media Flaws
Granted: November 6, 2014
Application Number:
20140331108
An apparatus for detecting media flaws includes a branch metric selection circuit operable to select a first branch metric and a second branch metric, a subtraction circuit operable to subtract the second branch metric from the first branch metric to yield a difference, and a comparator operable to compare the difference with a threshold value and to indicate a presence of a potential flaw in a storage medium when the difference is less than the threshold value.
Cross-Decoding for Non-Volatile Storage
Granted: November 6, 2014
Application Number:
20140331096
Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to…
Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads
Granted: October 9, 2014
Application Number:
20140304562
A SCAN chain architecture for each path in a circuit having combinational paths includes a control mechanism to control one or more flip flops and multiplexers to direct operational or test signals. Operational signals are sent along at least one combinational path to a pull-up/pull-down for at least one input/output pad and an operational voltage is recorded. Test signals are sent along at least one alternative path to an alternative input/output and a test voltage is recorded. The…
METHODS AND SYSTEMS FOR PERFORMING DEDUPLICATION IN A DATA STORAGE SYSTEM
Granted: October 9, 2014
Application Number:
20140304464
A dedupe cache solution is provided that uses an in-line signature generation algorithm on the front-end of the data storage system and an off-line dedupe algorithm on the back-end of the data storage system. The in-line signature generation algorithm is performed as data is moved from the system memory device of the host system into the DRAM device of the storage controller. Because the signature generation algorithm is an in-line process, it has very little if any detrimental impact on…
TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY
Granted: October 9, 2014
Application Number:
20140301143
In operation, respective lifetime expectancy scores are calculated for each of a plurality of blocks of a memory based on a respective count percentage of free space of each of the blocks. The blocks are recycled based on at least some of the life expectancy scores. A total amount of the blocks that are re-written is minimized while equalizing lifetime expectancy score variation between the blocks.
Priori Information Based Post-Processing in Low-Density Parity-Check Code Decoders
Granted: October 2, 2014
Application Number:
20140298131
A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.
Generating Partially Sparse Generator Matrix for a Quasi-Cyclic Low-Density Parity-Check Encoder
Granted: October 2, 2014
Application Number:
20140298129
A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H?; and constructing the generator matrix G based on the rearranged parity check matrix H?.
Scan Chain Reconfiguration and Repair
Granted: October 2, 2014
Application Number:
20140298123
A system includes an integrated circuit. The integrated circuit includes at least one scan chain group. A particular scan chain group of the at least one scan chain group includes at least one scan chain and at least one spare scan chain. The at least one scan chain of the particular scan chain group includes a particular scan chain. The at least one spare scan chain of the particular scan chain group includes a particular spare scan chain. The particular spare scan chain is configured…
Operational Amplifier-Based Current-Sensing Circuit for DC-DC Voltage Converters and The Like
Granted: October 2, 2014
Application Number:
20140292298
In one embodiment, an integrated circuit comprising a current-sensing circuit having a power transistor and an amplifier. The current-sensing circuit is coupled to (i) sense a current supplied to a load by a voltage source through an inductor and (ii) generate an inductor-current signal based on the sensed current. The current-sensing circuit includes: a power transistor and a sensing transistor, both coupled to receive an input voltage from the voltage source. The error amplifier has…
