Operational Amplifier-Based Current-Sensing Circuit for DC-DC Voltage Converters and The Like
Granted: October 2, 2014
Application Number:
20140292298
In one embodiment, an integrated circuit comprising a current-sensing circuit having a power transistor and an amplifier. The current-sensing circuit is coupled to (i) sense a current supplied to a load by a voltage source through an inductor and (ii) generate an inductor-current signal based on the sensed current. The current-sensing circuit includes: a power transistor and a sensing transistor, both coupled to receive an input voltage from the voltage source. The error amplifier has…
Systems and Methods for Reduced Constraint Code Data Processing
Granted: September 25, 2014
Application Number:
20140289582
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
Integrated Clock Architecture for Improved Testing
Granted: September 25, 2014
Application Number:
20140289550
A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing…
Dynamic Log Likelihood Ratio Quantization for Solid State Drive Controllers
Granted: September 25, 2014
Application Number:
20140289450
A method for system for dynamic channel Log Likelihood Ratio (LLR) quantization for a Solid State Drive (SSD) controller is a targeted approach to scaling which results in a scaled, quantized set of LLRs whose relative magnitude remains undisturbed from an original magnitude. The method reads a set of voltages from each channel of the SSD. The set of reads is configured in location and number for performance. Once a set is returned, the method determines an LLR for each of the voltages…
Systems and Methods for Multi-Dimensional Signal Equalization
Granted: September 25, 2014
Application Number:
20140286385
Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for equalizing a data signal.
Automatic On-Drive Sync-Mark Search and Threshold Adjustment
Granted: September 25, 2014
Application Number:
20140286149
A hard disk drive includes a processor to automatically adjust a threshold level for finding sync-marks. The processor determines all possible sync-mark patterns for a particular pattern length and analyzes each pattern with reference to real world data. The pattern with the largest distance gap is used. The threshold level is then adjusted dynamically to produce the lowest possible failure rate for the given pattern.
Method of Optimizing Solid State Drive Soft Retry Voltages
Granted: September 25, 2014
Application Number:
20140286102
A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for…
SYSTEMS AND METHODS FOR QUALITY BASED BIT ERROR RATE PREDICTION
Granted: September 25, 2014
Application Number:
20140285918
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for bit error rate prediction in a data processing system.
ADAPTIVE CONTINUOUS TIME LINEAR EQUALIZER
Granted: September 18, 2014
Application Number:
20140269888
An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response…
LINEAR PHASE FIR BIORTHOGONAL WAVELET FILTERS WITH COMPLEMENTARITY FOR IMAGE NOISE REDUCTION
Granted: September 18, 2014
Application Number:
20140280417
In described embodiments, Linear Phase, Finite Impulse Response, filters incorporate a power complementarity property into a perfect reconstruction filter bank. Non-linear constraints for type A and type B filters are included in the Sequential Quadratic Programming design of the filters. An initial Quadrature Mirror Filter includes perfect reconstruction constraints, which might be optimized through iterative design techniques. Embodiments might be employed in noise reduction…
BIASED BANG-BANG PHASE DETECTOR FOR CLOCK AND DATA RECOVERY
Granted: September 18, 2014
Application Number:
20140266338
An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a…
NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE
Granted: September 18, 2014
Application Number:
20140269053
A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more…
RETENTION DETECTION AND/OR CHANNEL TRACKING POLICY IN A FLASH MEMORY BASED STORAGE SYSTEM
Granted: September 18, 2014
Application Number:
20140269048
A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.
Systems and Methods for P-Distance Based Priority Data Processing
Granted: September 18, 2014
Application Number:
20140268401
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
Systems and Methods for Loop Feedback
Granted: September 18, 2014
Application Number:
20140268400
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing loop feedback in a data processing system.
Hardware Support of Servo Format with Two Preamble Fields
Granted: September 18, 2014
Application Number:
20140268397
A hard disk drive uses a second, reference burst field in a preamble to estimate burst phase and burst magnitude. Such estimations are used for position error signal integration and repeatable runout correction. Gain error is also derived from such estimations. Information contained in a preamble field is used in conjunction with the reference burst phase estimation to synchronize servo address marks.
INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION
Granted: September 18, 2014
Application Number:
20140266820
In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an…
LEMPEL-ZIV DATA COMPRESSION WITH SHORTENED HASH CHAINS BASED ON REPETITIVE PATTERNS
Granted: September 18, 2014
Application Number:
20140266815
Methods and apparatus are provided for Lempel-Ziv data compression with shortened hash chains based on repetitive multi-byte runs. Data is compressed by processing a sequence of data to identify a repetitive pattern, such as a multi-byte run; and providing indicators associated with the sequence of data of a start position and an end position of the repetitive pattern. The indicators of the start and end positions of the repetitive pattern may comprise, for example, flags associated with…
AC COUPLING CIRCUIT WITH HYBRID SWITCHES AND CONSTANT LOAD
Granted: September 18, 2014
Application Number:
20140266497
A coupling apparatus having plurality of branches and a resistive element is disclosed. Each branch may be configured to couple at least one of (i) a first input node and (ii) a second input node to a first output node through a plurality of switches and a plurality of capacitors. The resistive element generally connects the first output node to a second output node. The first output node may be loaded by a respective parasitic capacitance of at least one of the switches.
AC COUPLING CIRCUIT WITH HYBRID SWITCHES
Granted: September 18, 2014
Application Number:
20140266395
A coupling apparatus having a first branch and a second branch is disclosed. The first branch generally comprises (A) a first switch group configured to connect an input signal to an output node through a first capacitor, and (B) second switch group configured to connect either (i) a second signal, or (ii) a ground voltage, to the output node through a second capacitor. The second branch generally comprises (A) a third switch group configured to connect the input signal to the output…
