Lock-Free Communication Storage Request Reordering
Granted: September 18, 2014
Application Number:
20140281171
Lock-free communication storage request reordering enables reduced latency and/or increased bandwidth in some usage scenarios, such as a multi-threaded driver context operating with a device, such as a storage device (e.g. a Solid-State Disk (SSD)) enabled to respond to a multiplicity of outstanding requests.
TAMPER SENSOR
Granted: September 18, 2014
Application Number:
20140283146
A deformable tamper sensor and tamper resistant electronic system is operable to detect opening of an enclosure and perform actions responsive to the detection. Movable elements within the tamper sensor are held in position when the sensor is compressed and define a multi-bit sensor value. Transitioning the sensor from a compressed to a non-compressed state non-destructively provides a new sensor value through movement of one or more elements.
Systems and Methods for Sync Mark Mis-Detection Protection
Granted: September 18, 2014
Application Number:
20140281841
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.
METHOD AND APPARATUS FOR GENERATION OF SOFT DECISION ERROR CORRECTION CODE INFORMATION
Granted: September 18, 2014
Application Number:
20140281822
A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the…
Method for Format Savings in Coherently Written Fragmented Sectors
Granted: September 18, 2014
Application Number:
20140281818
A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to…
Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder
Granted: September 18, 2014
Application Number:
20140281787
Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder.
RECOVERY STRATEGY THAT REDUCES ERRORS MISIDENTIFIED AS RELIABLE
Granted: September 18, 2014
Application Number:
20140281767
A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window; and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and…
Local Repair Signature Handling for Repairable Memories
Granted: September 18, 2014
Application Number:
20140281703
A method is disclosed for independent repair signature load into a repairable memory within a chip set of a design without halting operation of other repairable memories within the design. At initial power up, the repair signature is received from nonvolatile memory and parallelly stored within a memory repair register and within a local memory repair shadow register. During intermediate power ups after an operational power savings scheme shut down, the method avoids serially re-loading…
METHOD AND SYSTEM OF DATA RECOVERY IN A RAID CONTROLLER
Granted: September 18, 2014
Application Number:
20140281688
Disclosed is a system and method for providing data integrity for pinned cache even if a RAID controller card fails while it has pinned cache or a memory module goes bad. A controller is enabled to use complete cache lines even if pinned cache is present, thereby enabling other virtual disks to run in write-back mode when pinned cache is present.
Device Sleep Partitioning and Keys
Granted: September 18, 2014
Application Number:
20140281627
A data storage device includes a device sleep state pin and device sleep state logic to allow the data storage device to store security keys and necessary device sleep state logic together in a volatile logical data storage element. The volatile logical data storage element may be on-chip or off-chip. Device sleep state logic parameters for powering down PHYs while in a device sleep state determine the power characteristics of the device sleep state.
Systems and Methods for P-Distance Based Priority Data Processing
Granted: September 18, 2014
Application Number:
20140268401
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
REDUCING FLASH MEMORY WRITE AMPLIFICATION AND LATENCY
Granted: September 18, 2014
Application Number:
20140281143
Data is distributed to solid-state disks (SSDs) using the RAID-0 technique. Based on a utilization of a first region of a first one of the SSDs, the first region is selected for garbage collection. Valid data from the first region is copied to an active region of the first one of the SSDs as part of a process of garbage collection. While the process of garbage collection is being performed, data is distributed to a subset of the SSDs using the RAID-0 technique where the subset of the…
DIRECT ROUTING BETWEEN ADDRESS SPACES THROUGH A NONTRANSPARENT PERIPHERAL COMPONENT INTERCONNECT EXPRESS BRIDGE
Granted: September 18, 2014
Application Number:
20140281106
A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and…
ENHANCED QUEUE MANAGEMENT
Granted: September 18, 2014
Application Number:
20140281083
A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response…
UNIFIED MESSAGE-BASED COMMUNICATIONS
Granted: September 18, 2014
Application Number:
20140281057
A system includes a plurality of processors, a message fabric, and a plurality of hardware units. Each of the plurality of processors comprises a plurality of communication FIFOs and has an instruction set including at least one instruction to send a message via at least one of the plurality of communication FIFOs. The message fabric couples the processors via at least some of the plurality of communication FIFOs. Each of the processors is associated with a respective one or more of the…
Efficient Hardware Structure For Sorting/Adding Multiple Inputs Assigned To Different Bins
Granted: September 18, 2014
Application Number:
20140280429
In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted to add together (a.k.a. accumulate) the numeric values of only those inputs signals having addresses that are the same. In particular, the inputs and outputs of the two-input, two-output…
LINEAR PHASE FIR BIORTHOGONAL WAVELET FILTERS WITH COMPLEMENTARITY FOR IMAGE NOISE REDUCTION
Granted: September 18, 2014
Application Number:
20140280417
In described embodiments, Linear Phase, Finite Impulse Response, filters incorporate a power complementarity property into a perfect reconstruction filter bank. Non-linear constraints for type A and type B filters are included in the Sequential Quadratic Programming design of the filters. An initial Quadrature Mirror Filter includes perfect reconstruction constraints, which might be optimized through iterative design techniques. Embodiments might be employed in noise reduction…
ADAPTIVE CONTINUOUS TIME LINEAR EQUALIZER
Granted: September 18, 2014
Application Number:
20140269888
An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response…
NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE
Granted: September 18, 2014
Application Number:
20140269053
A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more…
RETENTION DETECTION AND/OR CHANNEL TRACKING POLICY IN A FLASH MEMORY BASED STORAGE SYSTEM
Granted: September 18, 2014
Application Number:
20140269048
A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.
