Efficient Hardware Structure For Sorting/Adding Multiple Inputs Assigned To Different Bins
Granted: September 18, 2014
Application Number:
20140280429
In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted to add together (a.k.a. accumulate) the numeric values of only those inputs signals having addresses that are the same. In particular, the inputs and outputs of the two-input, two-output…
PREEMPTIVE CONNECTION SWITCHING FOR SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE SYSTEMS
Granted: September 11, 2014
Application Number:
20140258572
Methods and structure for preemptively terminating Serial Attached Small Computer System Interface connections are provided. One exemplary embodiment includes an expander comprising multiple physical links, switching circuitry able to establish connections between end devices coupled with the expander through the physical links, and a connection manager. The connection manager is able to process an Open Address Frame from an end device, and to determine that the Open Address Frame…
PARTIAL R-BLOCK RECYCLING
Granted: September 11, 2014
Application Number:
20140258769
An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.
SYSTEM AND METHOD FOR DE-QUEUING AN ACTIVE QUEUE
Granted: September 11, 2014
Application Number:
20140258759
Aspects of the disclosure pertain to a system and method for de-queuing an active queue. The system promotes power efficiency by providing a mechanism for allowing some of its active queues to be de-queued and one or more of its processors associated with those active queues to be powered off during low traffic periods. Using fewer than all of its queues and processors, the system can handle incoming traffic during these low traffic periods without packet loss and without ordering…
STORAGE DEVICE POWER FAILURE INFRASTRUCTURE
Granted: September 11, 2014
Application Number:
20140258755
A power fail protection system wherein pluralities of individual energy storage components are electrically connected to one or more SSD drives during a power failure though a power switch matrix. Typically an individual high-energy supply will be connected to one SSD drive during a power failure. The power fail protection system may also test the transient energy response of individual energy storage components, or include an imminent power fail warning connected directly to an SSD…
SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM FOR MANAGING A CACHE STORE TO ACHIEVE IMPROVED CACHE RAMP-UP ACROSS SYSTEM REBOOTS
Granted: September 11, 2014
Application Number:
20140258628
A cache controller having a cache store and associated with a storage system maintains information stored in the cache store across a reboot of the cache controller. The cache controller communicates with a host computer system and a data storage system. The cache controller partitions the cache memory to include a metadata portion and log portion. A separate portion is used for cached data elements. The cache controller maintains a copy of the metadata in a separate memory accessible to…
VOLUME CHANGE FLAGS FOR INCREMENTAL SNAPSHOTS OF STORED DATA
Granted: September 11, 2014
Application Number:
20140258613
Methods and structure are provided for tracking changes to a logical volume over time. One exemplary embodiment is a backup system for a Redundant Array of Independent Disks (RAID) storage system. The backup system includes a backup storage device that includes Copy-On-Write snapshots of a logical volume of the storage system. The backup system also includes a backup controller. The backup controller is able to maintain flags for the logical volume that indicate whether extents at the…
SCALABLE STORAGE DEVICES
Granted: September 11, 2014
Application Number:
20140258598
Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process…
SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM FOR DYNAMIC CACHE SHARING IN A FLASH-BASED CACHING SOLUTION SUPPORTING VIRTUAL MACHINES
Granted: September 11, 2014
Application Number:
20140258595
A cache controller implemented in O/S kernel, driver and application levels within a guest virtual machine dynamically allocates a cache store to virtual machines for improved responsiveness to changing demands of virtual machines. A single cache device or a group of cache devices are provisioned as multiple logical devices and exposed to a resource allocator. A core caching algorithm executes in the guest virtual machine. As new virtual machines are added under the management of the…
SELF RECOVERY IN A SOLID STATE DRIVE
Granted: September 11, 2014
Application Number:
20140258587
An apparatus having a nonvolatile memory and a controller. The memory stores information in multiple pages. The information includes data units and headers. Each data unit is associated with a respective identifier in an address space of the apparatus and a respective location in the memory, has a respective header having the respective identifier, and is associated with a respective time stamp. Multiple headers include ones of the time stamps. The controller is configured to (i) read…
PROGRAMMABLE CLOCK SPREADING
Granted: September 11, 2014
Application Number:
20140253203
An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient…
SMART DISCOVERY MODEL IN A SERIAL ATTACHED SMALL COMPUTER SYSTEM TOPOLOGY
Granted: September 11, 2014
Application Number:
20140258565
Methods, systems and processor-readable media are disclosed for implementing a “smart” discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators can be prevented from blocking input/output to particular components in communication with the data transfer regime, thereby improving and completing the discovery process in an optimal time frame…
SYSTEM AND METHOD FOR LARGE OBJECT CACHE MANAGEMENT IN A NETWORK
Granted: September 11, 2014
Application Number:
20140258375
Aspects of the disclosure pertain to a system and method for large object cache management in a network. A proxy server of the present disclosure implements a token-based policing mechanism via a cache tracking table to evaluate objects for potential inclusion in a cache controlled by the proxy server and to age-out objects already stored in the cache. Use of the tracking table and token-based policing mechanism by the proxy server promoting efficient usage of caching resources and…
TRANSMIT REFERENCE SIGNAL CLEANUP WITHIN A SYNCHRONOUS NETWORK APPLICATION
Granted: September 11, 2014
Application Number:
20140254735
A network processor is described that includes a network reference clock processor module for providing an at least substantially low-jitter, low-wander reference signal. In one or more embodiments, the network reference clock processor module includes a digital phase locked loop configured to at least substantially attenuate a wander noise portion from a reference signal. The network reference clock processor module also includes an analog phase locked loop communicatively coupled to…
ADAPTATION OF EQUALIZER SETTINGS USING ERROR SIGNALS SAMPLED AT SEVERAL DIFFERENT PHASES
Granted: September 11, 2014
Application Number:
20140254655
An apparatus includes an error sample generating circuit and an adaptation circuit. The error sample generating circuit is generally configured to generate error samples at a plurality of phases. The adaptation circuit may be configured to adjust one or more equalizer settings based upon a data sample and the error samples.
NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL
Granted: September 11, 2014
Application Number:
20140254593
An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value…
SAMPLING-PHASE ACQUISITION BASED ON CHANNEL-IMPULSE-RESPONSE ESTIMATION
Granted: September 11, 2014
Application Number:
20140254043
Embodiments of the invention can be manifested as methods for converting analog waveforms into digital sampled signals. In at least one such embodiment, the method includes (i) sampling, based on a sampling-clock signal, an analog waveform received from a transmission channel to generate a digital sampled signal, (ii) generating a digital target signal by applying a specified reference data pattern to a model of the transmission channel, and (iii) adjusting the sampling-clock signal by…
Servo Marginalization
Granted: September 11, 2014
Application Number:
20140254041
Servo channel noise limits are defined through Viterbi decisions based on servo gate signals. Y values are used to produce a first Viterbi decision at each servo gate. Viterbi decisions and Y values are used to produce ideal Y values. Y values and ideal Y values are used to produce an error value which is adjusted by a noise factor based on estimated channel characteristics. The noise value is combined with Y values and used to produce a second Viterbi decision at each servo gate.
POWER INTEGRITY CONTROL THROUGH ACTIVE CURRENT PROFILE MANAGEMENT
Granted: September 11, 2014
Application Number:
20140253226
An apparatus having one or more of a plurality of circuits in a first level of a hierarchy and two or more of the circuits in a second level of the hierarchy is disclosed. The circuits are configured to (i) allocate a profile from the first level down to the second level, (ii) manage from the second level a respective power consumed by each of a plurality of blocks based on the profile and (iii) maintain a sum of the powers approximately constant by increasing the power consumed by a…
PREVENTING ELECTRONIC DEVICE COUNTERFEITS
Granted: September 11, 2014
Application Number:
20140253222
Systems and methods for authenticating electronic devices may perform one or more operations including, but not limited to: receiving at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for at least one electronic device; and blowing one or more fuses of the at least one electronic device according to the at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for the at least…
