Method for Storage Driven De-Duplication of Server Memory
Granted: July 24, 2014
Application Number:
20140207743
A method for storage driven de-duplication of server memory comprises configuring a storage controller, as part of each IO operation, to generate a unique signature for each data page passing through the controller. The method associates the signature with the data page and stores the associated page and signature. The signature is added to a signature queue for signature match analysis with signatures stored in server memory. Signature analysis is limited to read-only pages to speed up…
METHOD AND APPARATUS FOR MPEG-2 TO H.264 VIDEO TRANSCODING
Granted: July 24, 2014
Application Number:
20140205005
A method for transcoding from an MPEG-2 format to an H.264 format is disclosed. The method generally comprises the steps of (A) decoding an input video stream in the MPEG-2 format to generate a plurality of macroblocks; (B) determining a plurality of indicators from a pair of the macroblocks, the pair of the macroblocks being vertically adjoining; and (C) coding the pair of the macroblocks into an output video stream in the H.264 format using one of (i) a field mode coding and (ii) a…
EFFICIENT REGION OF INTEREST DETECTION
Granted: July 24, 2014
Application Number:
20140204995
An apparatus having a circuit is disclosed. The circuit may be configured to (i) calculate a plurality of complexity values while compressing a current picture in a video signal. Each complexity value generally characterizes how a corresponding one of a plurality of blocks in the current picture was compressed. The circuit may also be configured to (ii) adjust the complexity values below a first threshold to a default value and (iii) generate a region of interest by grouping the blocks…
System and Method for Determining Channel Loss in a Dispersive Communication Channel at the Nyquist Frequency
Granted: July 24, 2014
Application Number:
20140204987
The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver…
MARGIN FREE PVT TOLERANT FAST SELF-TIMED SENSE AMPLIFIER RESET CIRCUIT
Granted: July 24, 2014
Application Number:
20140204683
In described embodiments, a circuit for providing a margin free PVT tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second PMOS drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal, a read detect block…
MEMORY HAVING SENSE AMPLIFIER FOR OUTPUT TRACKING BY CONTROLLED FEEDBACK LATCH
Granted: July 24, 2014
Application Number:
20140204660
In described embodiments, a memory circuit includes a static random access memory (SRAM) including N banks of memory cells, rows of M sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, a dummy output latch coupled to the pull-down select block to store the read data, and a SRAM reset generation circuit coupled to the sense amplifier control…
CAPACITIVE COUPLED SENSE AMPLIFIER BIASED AT MAXIMUM GAIN POINT
Granted: July 24, 2014
Application Number:
20140204659
A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first…
Subtractive Validation of Cache Lines for Virtual Machines
Granted: July 17, 2014
Application Number:
20140201462
A method and system for managing a cache for a host machine is disclosed. The method includes: indicating each cache line in the cache as being in a transitional meta-state when any virtual machine hosted on the host machine moves out of the host machine; each time a particular cache line is accessed, indicating that particular cache line as no longer in the transitional meta-state; and marking the cache lines still in the transitional meta-state as invalid when a virtual machine moves…
State-Split Based Endec
Granted: July 17, 2014
Application Number:
20140201585
Various embodiments of the present invention provide systems and methods for encoding and decoding data for constrained systems with state-split based encoders and decoders.
SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIATED RESET MULTIPLEXING CIRCUITRY
Granted: July 17, 2014
Application Number:
20140201584
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises control circuitry configured to control selective application of at least a particular one of a plurality of reset signals to reset inputs of at least a subset of the scan cells of the scan chain. For example, the control…
CACHE BASED STORAGE CONTROLLER
Granted: July 17, 2014
Application Number:
20140201442
Systems and techniques for continuously writing to a secondary storage cache are described. A data storage region of a secondary storage cache is divided into a first cache region and a second cache region. A data storage threshold for the first cache region is determined. Data is stored in the first cache region until the data storage threshold is met. Then, additional data is stored in the second cache region while the data stored in the first cache region is written back to a primary…
DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING
Granted: July 17, 2014
Application Number:
20140200849
Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.
LOW LATENCY IN-LINE DATA COMPRESSION FOR PACKET TRANSMISSION SYSTEMS
Granted: July 17, 2014
Application Number:
20140198789
Deep packet inspection (DPI) techniques are utilized to provide data compression, particularly necessary in many bandwidth-limited communication systems. A separate processor is initially used within a transmission source to scan, in real time, a data packet stream and recognize repetitive patterns that are occurring in the data. The processor builds a dictionary (ruleset), storing the set, of repetitive patterns and defining a unique token ID to be associated with each pattern.…
Systems and Methods for Loop Processing With Variance Adaptation
Granted: July 17, 2014
Application Number:
20140198405
Systems and methods for data processing, and more particularly systems and methods for loop processing with variance adaptation.
SYSTEMS AND METHODS FOR X-SAMPLE BASED NOISE CANCELLATION
Granted: July 17, 2014
Application Number:
20140198404
Systems, methods, devices, circuits for data processing, and more particularly to cancelling noise while processing data.
BICMOS GATE DRIVER FOR CLASS-S RADIO FREQUENCY POWER AMPLIFIER
Granted: July 10, 2014
Application Number:
20140191801
The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the…
RECEIVER WITH DUAL CLOCK RECOVERY CIRCUITS
Granted: July 10, 2014
Application Number:
20140192935
A receiver derives the desired data sampling clock phase by averaging the phase information of transitions before and after a data eye. The average of the phase information reduces data clock phase error due to variations in the phases of transitions in received data signals depending on the polarity and positions of the transitions.
ULTRA-WIDEBAND LOSS OF SIGNAL DETECTOR AT A RECEIVER IN A HIGH SPEED SERIALIZER/DESERIALIZER (SERDES) APPLICATION
Granted: July 10, 2014
Application Number:
20140192841
An apparatus comprising a first loss of signal circuit, a second loss of a signal circuit and a gate circuit. The first loss of a signal circuit may be configured to (i) receive an input signal containing a series of data and (ii) generate a first indication signal when the input signal is operating within a first frequency range. The second loss of signal circuit may be configured to (i) receive the input signal and (ii) generate a second indication signal when the input signal is…
SYSTEM AND METHOD FOR PROVIDING FAST AND EFFICIENT FLUSHING OF A FORWARDING DATABASE IN A NETWORK PROCESSOR
Granted: July 10, 2014
Application Number:
20140192633
Aspects of the disclosure pertain to a system and method for providing fast and efficient flushing of a forwarding database in a network processor. The present disclosure provides a deterministic mechanism to implement a flush operation for flushing the forwarding database. A dual FDB approach, a means for switching from one FDB to another in the event of a failure, and FDB flush operation as a background task are key features of this disclosure. The effective time for completing the…
DIFFERENTIAL SENSE AMPLIFIER FOR SOLID-STATE MEMORIES
Granted: July 10, 2014
Application Number:
20140192603
Described embodiments provide a memory having at least one sense amplifier with inputs coupled to at least one pair of bit lines. One of the pair of bit lines is precharged to a power supply voltage and a second one of the pair is precharged to ground. A first switch DC-couples the first one of the pair of bit lines to a first input of a cross-coupled amplifier. A first capacitor AC-couples the second one of the pair of bit lines to a second input of the cross-coupled amplifier. Then a…
