RECEIVER WITH DUAL CLOCK RECOVERY CIRCUITS
Granted: July 10, 2014
Application Number:
20140192935
A receiver derives the desired data sampling clock phase by averaging the phase information of transitions before and after a data eye. The average of the phase information reduces data clock phase error due to variations in the phases of transitions in received data signals depending on the polarity and positions of the transitions.
ULTRA-WIDEBAND LOSS OF SIGNAL DETECTOR AT A RECEIVER IN A HIGH SPEED SERIALIZER/DESERIALIZER (SERDES) APPLICATION
Granted: July 10, 2014
Application Number:
20140192841
An apparatus comprising a first loss of signal circuit, a second loss of a signal circuit and a gate circuit. The first loss of a signal circuit may be configured to (i) receive an input signal containing a series of data and (ii) generate a first indication signal when the input signal is operating within a first frequency range. The second loss of signal circuit may be configured to (i) receive the input signal and (ii) generate a second indication signal when the input signal is…
SYSTEM AND METHOD FOR PROVIDING FAST AND EFFICIENT FLUSHING OF A FORWARDING DATABASE IN A NETWORK PROCESSOR
Granted: July 10, 2014
Application Number:
20140192633
Aspects of the disclosure pertain to a system and method for providing fast and efficient flushing of a forwarding database in a network processor. The present disclosure provides a deterministic mechanism to implement a flush operation for flushing the forwarding database. A dual FDB approach, a means for switching from one FDB to another in the event of a failure, and FDB flush operation as a background task are key features of this disclosure. The effective time for completing the…
DIFFERENTIAL SENSE AMPLIFIER FOR SOLID-STATE MEMORIES
Granted: July 10, 2014
Application Number:
20140192603
Described embodiments provide a memory having at least one sense amplifier with inputs coupled to at least one pair of bit lines. One of the pair of bit lines is precharged to a power supply voltage and a second one of the pair is precharged to ground. A first switch DC-couples the first one of the pair of bit lines to a first input of a cross-coupled amplifier. A first capacitor AC-couples the second one of the pair of bit lines to a second input of the cross-coupled amplifier. Then a…
BICMOS GATE DRIVER FOR CLASS-S RADIO FREQUENCY POWER AMPLIFIER
Granted: July 10, 2014
Application Number:
20140191801
The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the…
MULTI-DIE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF
Granted: July 10, 2014
Application Number:
20140191403
A multi-die semiconductor package and various methods of manufacturing the same. In one embodiment, the semiconductor package includes: (1) a substrate, (2) a first die coupled to the substrate, the first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC) that substantially occupies an area of the first die, (3) a second die coupled to the substrate, the second die having a second set of terminals and bearing a second IC that…
SERDES DATA SAMPLING GEAR SHIFTER
Granted: July 3, 2014
Application Number:
20140185658
A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the…
MANAGEMENT OF DEVICE FIRMWARE UPDATE EFFECTS AS SEEN BY A HOST
Granted: July 3, 2014
Application Number:
20140189673
Management of device firmware update effects as seen by a computing host enables continuously running an OS on the host across a device firmware update, e.g., via delaying visibility of at least a portion of effects of the firmware update, such as in a context where without the delay in visibility the OS would encounter an unrecoverable error and crash. For example, a device (e.g. an SSD) is coupled to a computing host running an unmodified version of Windows. Firmware on the device is…
Non-Volatile Memory Program Failure Recovery Via Redundant Arrays
Granted: July 3, 2014
Application Number:
20140189421
Non-volatile memory program failure recovery via redundant arrays enables higher programming bandwidth and/or reduced latency in some storage subsystem implementations, e.g. a solid-state disk. Data to program N portions of a plurality of non-volatile memories is received at a non-volatile memory controller. The data includes particular data to program a particular one of the N portions. The particular data is stored in an allocated buffer associated with the non-volatile memory…
Efficient Algorithm to Bit Matrix Symmetry
Granted: July 3, 2014
Application Number:
20140188969
An algorithm that maintains the symmetry of a symmetric bit matrix stored in computer memory without having to process all of the elements of a transpose column by considering only the elements changed in a row. The algorithm operates on groups of bits forming rows of the matrix rather than processing the individual bit elements of the matrix. Instead of checking whether each bit needs to be modified, the algorithm toggles only the column bits that are the transpose elements of modified…
PRE-CHARGE TRACKING OF GLOBAL READ LINES IN HIGH SPEED SRAM
Granted: July 3, 2014
Application Number:
20140185366
In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output…
SYNC MARK DETECTION USING BRANCH METRICS FROM DATA DETECTOR
Granted: July 3, 2014
Application Number:
20140185159
Methods and apparatus are provided for detecting a sync mark in a storage system, such as a hard disk drive. A sync mark is detected in a storage system by obtaining one or more branch metrics from a data detector in the storage system; generating one or more sync mark metrics using the one or more branch metrics from the data detector; and identifying the sync mark based on the sync mark metrics. An input data set is optionally compared with a plurality of portions of a sync mark…
FLY HEIGHT CONTROL FOR HARD DISK DRIVES
Granted: July 3, 2014
Application Number:
20140185158
A fly height control circuit includes an input node to receive a digital control signal, an output node to output a control current to a resistive heater element to adjust a spacing between a read/write head and a surface of a storage medium, and control circuitry to process the digital control signal and generate the output control current based on the digital control signal. The control circuitry generates a first reference current based at least in part on the control current output…
Hybrid Digital/Analog Power Amplifier
Granted: July 3, 2014
Application Number:
20140184323
The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance…
High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices
Granted: June 26, 2014
Application Number:
20140176230
A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias…
SINGLE SERDES TRANSMITTER DRIVER DESIGN FOR BOTH ETHERNET AND PERIPHERAL COMPONENT INTERCONNECT EXPRESS APPLICATIONS
Granted: June 26, 2014
Application Number:
20140181845
An apparatus includes a first coding circuit, a second coding circuit, and a plurality of source series terminated driver slices. The first coding circuit may be configured to generate a plurality of digital filter control codes in response to a plurality of filter coefficients and a control signal. The control signal selects between a plurality of communication specifications. The second coding circuit may be configured to generate a plurality of driver slice control codes in response…
SUSPEND SDRAM REFRESH CYCLES DURING NORMAL DDR OPERATION
Granted: June 26, 2014
Application Number:
20140177371
An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.
Single-Port Read Multiple-Port Write Storage Device Using Single-Port Memory Cells
Granted: June 26, 2014
Application Number:
20140177324
A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The…
EQUALIZATION COMBINING OUTPUTS OF MULTIPLE COMPONENT FILTERS
Granted: June 26, 2014
Application Number:
20140177087
An apparatus comprises read channel circuitry and associated signal processing circuitry. The signal processing circuitry comprises: an equalizer configured to combine an output of two or more component filters into a single equalized data signal; a detector with an input coupled to an output of the equalizer configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal; a decoder with an input coupled to an output…
Systems and Methods for Managed Operational Marginalization
Granted: June 26, 2014
Application Number:
20140177084
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.
