I/O DEVICE AND COMPUTING HOST INTEROPERATION
Granted: June 26, 2014
Application Number:
20140181327
An I/O device is coupled to a computing host. In some embodiments, the device is enabled to utilize memory of the computing host not directly coupled to the device to store information such as a shadow copy of a map of the device and/or state of the device. Storage of the shadow copy of the map enables one or both of the device and the computing host to utilize the shadow copy of the map, such as to decrease read latency. Storage of the state enables the device to save volatile state…
SUSPEND SDRAM REFRESH CYCLES DURING NORMAL DDR OPERATION
Granted: June 26, 2014
Application Number:
20140177371
An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.
Single-Port Read Multiple-Port Write Storage Device Using Single-Port Memory Cells
Granted: June 26, 2014
Application Number:
20140177324
A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The…
EQUALIZATION COMBINING OUTPUTS OF MULTIPLE COMPONENT FILTERS
Granted: June 26, 2014
Application Number:
20140177087
An apparatus comprises read channel circuitry and associated signal processing circuitry. The signal processing circuitry comprises: an equalizer configured to combine an output of two or more component filters into a single equalized data signal; a detector with an input coupled to an output of the equalizer configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal; a decoder with an input coupled to an output…
Systems and Methods for Managed Operational Marginalization
Granted: June 26, 2014
Application Number:
20140177084
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.
OVER-SAMPLED SIGNAL EQUALIZER
Granted: June 26, 2014
Application Number:
20140177082
An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize an oversampled digital data signal to determine an equalized digital data signal, filter the equalized digital data signal, determine a hard decision and reliability of the filtered digital data signal, and decode the filtered digital data signal based at least in part on the hard decision and reliability. The…
ADAPTIVE CONTROL MECHANISMS TO CONTROL INPUT AND OUTPUT COMMON-MODE VOLTAGES OF DIFFERENTIAL AMPLIFIER CIRCUITS
Granted: June 26, 2014
Application Number:
20140176239
An amplifier circuit includes differential input nodes, a differential amplifier stage having differential input terminals and differential output terminals, and an input common-mode voltage adaptation circuit connected between the differential input nodes of the amplifier circuit and the differential input terminals of the differential amplifier stage. During an input common-mode adaptation phase, the input common-mode voltage adaptation circuit forces the differential input terminals…
High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices
Granted: June 26, 2014
Application Number:
20140176230
A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias…
VALIDATING OPERATION OF SYSTEM-ON-CHIP CONTROLLER FOR STORAGE DEVICE USING PROGRAMMABLE STATE MACHINE
Granted: June 19, 2014
Application Number:
20140173346
A system-on-chip includes a storage controller, a read channel integrated circuit, a programmable state machine controller, a switching circuit, a buffer memory, and an interface to access the buffer memory. The switching circuit connects the storage controller or the programmable state machine controller to the read channel integrated circuit. The interface is used to store test control data in the buffer memory. In a given test mode, the switching circuit switchably connects the…
MULTIPLE STEP NON-DETERMINISTIC FINITE AUTOMATON MATCHING
Granted: June 19, 2014
Application Number:
20140173603
Disclosed is a hardware NFA cell array used to find matches to regular expressions or other rules in an input symbol stream scans multiple symbols per clock cycle by comparing multiple symbol classes against multiple input symbols per cycle in parallel, signaling bundles of multiple transitions from parent cells to child cells and updating NFA state status by multiple steps. To retain high frequency operation, the cell array will not resolve transition chains from a first cell to a…
TAG MULTIPLICATION VIA A PREAMPLIFIER INTERFACE
Granted: June 19, 2014
Application Number:
20140168809
An apparatus having a controller and a preamplifier is disclosed. The controller may be configured to generate information on a serial bus coupled to a preamplifier interface. The preamplifier may be configured to (i) generate a count value in response to a clock signal synchronized to a recording medium and (ii) generate a plurality of tag signals based on the information and the count value. The tag signals may gate a read operation and a write operation of the preamplifier.
PROCESSOR CONFIGURED FOR OPERATION WITH MULTIPLE OPERATION CODES PER INSTRUCTION
Granted: June 19, 2014
Application Number:
20140173256
A method of associating operation codes with instructions for execution in a processor includes the steps of assigning the operation codes to the instructions in a manner that allows a given instruction to have multiple assigned operation codes and selecting a particular one of the multiple assigned operation codes for use in executing a program containing the given instruction. The assigning step may be implemented in conjunction with design of the processor, and may further comprise…
Method and Apparatus to Share a Single Storage Drive Across a Large Number of Unique Systems When Data is Highly Redundant
Granted: June 19, 2014
Application Number:
20140172797
A boot appliance for writing data to a particular host system's boot image and returning boot image data to a particular host system of a plurality of host systems. The boot appliance includes at least one storage medium, wherein the at least one storage medium is configured to store a base boot image and a plurality of variance boot images. The boot appliance further includes a buffer. The base boot appliance also includes a computer readable medium embodying computer code configured to…
PICTURE REFRESH WITH CONSTANT-BIT BUDGET
Granted: June 19, 2014
Application Number:
20140169468
An apparatus having a memory and a circuit is disclosed. The memory may be configured to store multiple reference pictures. The circuit may be configured to (i) generate multiple compressed pictures by compressing each uncompressed picture using the reference pictures and a constant-bit budget and (ii) generate multiple new reference pictures in the memory by decompressing the compressed pictures. A subset of the compressed pictures may each be divided into a first area, a second area…
PERFORMANCE CONTROL IN VIDEO ENCODING
Granted: June 19, 2014
Application Number:
20140169457
An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a complexity value by encoding a current picture in a video signal, where the current picture is encoded using a current one of a plurality of configurations, (ii) calculate an estimate in response to the complexity value and (iii) reconfigure the encoding into a new one of the configurations in response to the estimate relative to one or more thresholds. The configurations may include a normal…
ADAPTIVE CANCELLATION OF VOLTAGE OFFSET IN A COMMUNICATION SYSTEM
Granted: June 19, 2014
Application Number:
20140169440
Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock recovery.
RECEIVER WITH DISTORTION COMPENSATION CIRCUIT
Granted: June 19, 2014
Application Number:
20140169426
A receiver containing analog circuitry that generates distortion, a distortion compensation circuit coupled to an output of the analog circuitry, and a slicer, operating as a signal peak detector, coupled to the distortion compensation circuitry. The distortion compensation circuit has a subtractor, a function generator, and a weighting circuit. The subtractor has a first input coupled to the output of the analog circuitry, a second input, and an output. The function generator has an…
Link Rate Availability Based Arbitration
Granted: June 19, 2014
Application Number:
20140169210
The disclosure is directed to a system and method for managing connections across a plurality of phys including at least one phy having a first link rate and at least one phy having a second link rate. At least one connection request including a selected link rate is received from an initiator. An arbitration in progress (AIP) delay is provided when at least one phy having the selected link rate or higher is not available. During the AIP delay, a link manager continues to check for a phy…
Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling
Granted: June 19, 2014
Application Number:
20140168811
A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger…
Systems and Methods for Adaptive Threshold Pattern Detection
Granted: June 19, 2014
Application Number:
20140168810
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.
