MULTIPLE STEP NON-DETERMINISTIC FINITE AUTOMATON MATCHING
Granted: June 19, 2014
Application Number:
20140173603
Disclosed is a hardware NFA cell array used to find matches to regular expressions or other rules in an input symbol stream scans multiple symbols per clock cycle by comparing multiple symbol classes against multiple input symbols per cycle in parallel, signaling bundles of multiple transitions from parent cells to child cells and updating NFA state status by multiple steps. To retain high frequency operation, the cell array will not resolve transition chains from a first cell to a…
Low Density Parity Check Decoder With Dynamic Scaling
Granted: June 19, 2014
Application Number:
20140173385
A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check…
VALIDATING OPERATION OF SYSTEM-ON-CHIP CONTROLLER FOR STORAGE DEVICE USING PROGRAMMABLE STATE MACHINE
Granted: June 19, 2014
Application Number:
20140173346
A system-on-chip includes a storage controller, a read channel integrated circuit, a programmable state machine controller, a switching circuit, a buffer memory, and an interface to access the buffer memory. The switching circuit connects the storage controller or the programmable state machine controller to the read channel integrated circuit. The interface is used to store test control data in the buffer memory. In a given test mode, the switching circuit switchably connects the…
Split Brain Detection and Recovery System
Granted: June 19, 2014
Application Number:
20140173330
The invention provides for split brain detection and recovery in a DAS cluster data storage system through a secondary network interconnection, such as a SAS link, directly between the DAS controllers. In the event of a communication failure detected on the secondary network, the DAS controllers initiate communications over the primary network, such as an Ethernet used for clustering and failover operations, to diagnose the nature of the failure, which may include a crash of a data…
CACHE PREFETCH FOR DETERMINISTIC FINITE AUTOMATON INSTRUCTIONS
Granted: June 19, 2014
Application Number:
20140173254
In a DFA scanning engine used to match regular expressions or similar rules, instructions to execute DFA state transitions are accessed through an instruction cache. Each DFA instruction may indicate varying numbers of transitions or branches from a current state. The cache pre-fetches a requested number of additional instructions consecutively following an accessed instruction. The DFA engine accesses an instruction from the cache corresponding to a state within a small number of…
Expander for Loop Architectures
Granted: June 19, 2014
Application Number:
20140173165
An expander for a device architecture, such as a SAS-compatible expander for a SAS architecture, is configured to follow a set of discovery rules that are applied following detection of a discovery-triggering event, such as system power up or reset. According to one of the discovery rules, the expander waits until after a specified duration following the detected discovery-triggering event before passing on, to any other expanders, any requests to check the status of their discovery…
Systems and Methods for Data Retry Using Averaging Process
Granted: June 19, 2014
Application Number:
20140172934
Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing.
FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE
Granted: June 12, 2014
Application Number:
20140164868
An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the…
POLICY FOR READ OPERATIONS ADDRESSING ON-THE-FLY DECODING FAILURE IN NON-VOLATILE MEMORY
Granted: June 12, 2014
Application Number:
20140164881
An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access. The controller includes an error correction engine configured to perform an error correction on codewords read from the non-volatile memory, and, if the error correction fails, to perform one or more retry procedures. The controller is further…
ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY
Granted: June 12, 2014
Application Number:
20140164880
An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.
MULTIPLE-CLOCK, NOISE-IMMUNE SLICER WITH OFFSET CANCELLATION AND EQUALIZATION INPUTS
Granted: June 12, 2014
Application Number:
20140159807
A slicer circuit including an input differential is configured to amplify an input reference voltage received at a pair of differential input nodes and provide a differential output voltage at a pair of differential output nodes, and a regeneration latch configured to amplify the differential output voltage. A differential offset compensation voltage is applied to the differential output voltage to provide DC-offset cancellation. A differential equalization voltage is applied to the…
Low Density Parity Check Decoder With Miscorrection Handling
Granted: June 12, 2014
Application Number:
20140164866
A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a…
Master-Slave Expander Logging
Granted: June 12, 2014
Application Number:
20140164846
The invention provides a data storage topology that includes a master logging node where the event logs for all of the nodes may be stored on a consolidated basis. The master logging node is configured with a sufficient amount of reserved or additional data storage to accommodate the event logging requirement for the entire data storage topology. The other expanders in the topology may remain at a baseline model. The master logging medium may be an inexpensive persistent storage, such as…
METHODS AND STRUCTURE FOR USING REGION LOCKS TO DIVERT I/O REQUESTS IN A STORAGE CONTROLLER HAVING MULTIPLE PROCESSING STACKS
Granted: June 12, 2014
Application Number:
20140164715
Methods and structure within a storage controller for using region locks to efficiently divert an I/O request received from an attached host system to one of multiple processing stacks in the controller. A region lock module within the controller allows each processing stack to request a region lock for a range of block addresses of the storage devices. A divert-type lock request may be established to identify a range of block addresses for which I/O requests should be diverted to a…
STRUCTURE FOR NON-BLOCKING SERIAL ATTACHED SCSI INFRASTRUCTURE UTILIZING VIRTUAL PATHWAYS
Granted: June 12, 2014
Application Number:
20140164670
Structure is disclosed for a non-blocking SAS architecture utilizing virtual connections between SAS devices. One embodiment comprises a SAS expander. The SAS expander comprises a plurality of physical links (PHYs) and a Virtual Connection Manager (VCM) coupled with the plurality of PHYs. The VCM exchanges information over a plurality of concurrently established virtual pathways between a first PHY of the plurality of PHYs and a second PHY of the plurality of PHYs.
Load Balancing with SCSI I/O Referrals
Granted: June 12, 2014
Application Number:
20140164653
A method and/or system may be configured to receive an input/output (I/O) request from an initiator system, add priority information to a multiple path referral for each port on which data can be accessed, selectively omit ports on which data may be accessed, transmit the multiple path referral from the target to the initiator, and/or choose a path on the initiator with the highest performance.
NON-DETERMINISTIC FINITE AUTOMATON OVERFLOW RECOVERY
Granted: June 12, 2014
Application Number:
20140164309
Disclosed is a method of recovering from overflow of a hardware dynamically reconfigurable NFA cell array, to find matches within a symbol stream to regular expression or similar rules without missing matches due to overflow. Upon overflow, active states are selected to spill from the cell array, saving state information and spill position. Scanning continues a limited distance, with additional overflow spills possible, to a selected end of segment position where all active end states…
MULTI-LAYER APPROACH FOR FRAME-MISSING CONCEALMENT IN A VIDEO DECODER
Granted: June 12, 2014
Application Number:
20140161198
The invention relates to a method of concealing errors attributed to missing frames in a Motion Picture Expert Group-2 video stream, including the steps of: receiving a new frame for decoding and a “frame missing” flag that is set to a value associated with the occurrence of a missing frame, parsing the new frame to recover a picture type and a frame structure of the new frame, retrieving a picture type and a frame structure of a previous frame decoded immediately prior to the new…
Systems and Methods for X-Sample Based Data Processor Marginalization
Granted: June 12, 2014
Application Number:
20140160592
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.
SWITCHING POWER AMPLIFIER SYSTEM FOR MULTI-PATH SIGNAL INTERLEAVING
Granted: June 12, 2014
Application Number:
20140159991
A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to…
