Systems and Methods for Selective Retry Data Retention Processing
Granted: June 5, 2014
Application Number:
20140157074
Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for re-processing data sets not successfully processed during standard processing.
DYNAMIC SLICE RESIZING WHILE ENCODING VIDEO
Granted: June 5, 2014
Application Number:
20140153644
An apparatus having a plurality of processors is disclosed. The processors may be configured to (i) gather a plurality of statistics by encoding a current picture in a video signal, (ii) calculate a plurality of complexity values in response to both the statistics and a plurality of coefficients and (iii) partition a next picture in the video signal into a plurality of slices in response to the complexity values such that each of the slices has a similar coding complexity. The statistics…
PACKET DATA PROCESSOR IN A COMMUNICATIONS PROCESSOR ARCHITECTURE
Granted: June 5, 2014
Application Number:
20140153575
Described embodiments provide a network processor having a hardware accelerator that identifies a received packet and, based on a flow identification associated with the received packet, might pre-fetch pre-established portions of data from the received packet into local data memory (e.g., local data cache) for processing by a general purpose processor core. In addition to the packet data, the software necessary for the general-purpose processor core to process the data might also be…
Read Assist Scheme for Reducing Read Access Time in a Memory
Granted: June 5, 2014
Application Number:
20140153346
A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control…
Systems and Methods for Old Data Inter-track Interference Compensation
Granted: June 5, 2014
Application Number:
20140153126
Systems and methods for data processing, and more particularly to estimating or calculating interference between tracks on a storage medium.
CONCURRENT TRUE AND COMPLEMENT SIGNAL GENERATION
Granted: June 5, 2014
Application Number:
20140152366
A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates…
SENSE-AMPLIFIER LATCH HAVING SINGLE DATA INPUT
Granted: June 5, 2014
Application Number:
20140152345
A latch circuit comprises true and complement data nodes. During a setup period of a latching operation, true node setup circuitry draws the true data node toward an input data signal in parallel with complement node setup circuitry drawing the complement node upward toward a high-voltage reference source (VDD) when the data signal is low or downward toward a low-voltage reference source (VSS) when the data signal is high. After the setup period, true and complement clock signals are…
EXTERNAL COMPONENT-LESS PVT COMPENSATION SCHEME FOR IO BUFFERS
Granted: June 5, 2014
Application Number:
20140152341
Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror…
SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION
Granted: May 29, 2014
Application Number:
20140149812
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells. The scan test circuitry further comprises control circuitry comprising first switching elements configured to control selective application of respective scan input signals to respective scan inputs of respective ones of the plurality of scan chains and second…
REDUCTION OF METAL FILL INSERTION TIME IN INTEGRATED CIRCUIT DESIGN PROCESS
Granted: May 29, 2014
Application Number:
20140149953
Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circuit design system is stored. The metal fill data is purged from the placement and routing database. At least one change to layout data in the placement and routing database is implemented. The…
OVERSHOOT SUPPRESSION FOR INPUT/OUTPUT BUFFERS
Granted: May 29, 2014
Application Number:
20140145775
Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages.
Systems and Methods for Controlled Data Processor Operational Marginalization
Granted: May 29, 2014
Application Number:
20140149796
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.
METHOD AND SYSTEM FOR COPYBACK COMPLETION WITH A FAILED DRIVE
Granted: May 29, 2014
Application Number:
20140149787
Disclosed is a method and system for saving the copybacked data in a drive and continuing to rebuild on the same drive where the copy back was in progress when the online drive, where the copy back is not initiated, fails.
SYSTEM AND METHOD FOR PROVIDING A FLASH MEMORY CACHE INPUT/OUTPUT THROTTLING MECHANISM BASED UPON TEMPERATURE PARAMETERS FOR PROMOTING IMPROVED FLASH LIFE
Granted: May 29, 2014
Application Number:
20140149638
Aspects of the disclosure pertain to a system and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life. The mechanism restricts flash memory cache caching of inputs/outputs associated with Least Recently Used data and Most Recently Used data when a temperature of the flash memory is at or above a threshold temperature.
Method for Determining a Serial Attached Small Computer System Interface Topology
Granted: May 29, 2014
Application Number:
20140149624
A method for determining a topology based on input/output criteria includes selecting a predefined topology, measuring the fitness of the topology, and breeding individuals from the topology by combining elements from the fittest individuals. The topology is then updated with the new individuals and the fitness of the new topology is measured. Iterations continue similarly until certain criteria are met.
SATA Data Appliance for Providing SATA Hosts with Access to a Configurable Number of SATA Drives Residing in a SAS Topology
Granted: May 29, 2014
Application Number:
20140149614
A method and apparatus for providing a SATA host with access to multiple SATA drives is disclosed. The apparatus may include: an emulated port multiplier for presenting at least one logical drive to the SATA host; a mapping module for maintaining a mapping between the at least one logical drive and a plurality of physical SATA drives, wherein the plurality of physical SATA drives reside in a SAS topology; and a SATA/STP bridge for providing an interface between the SATA host and the SAS…
DFA-NFA HYBRID
Granted: May 29, 2014
Application Number:
20140149439
Disclosed is a hybrid architecture combining DFA and NFA based engines. The DFA engine and NFA engine scan the same input stream. The DFA engine may be a multi-threaded engine. Fragments of rules are assigned to the DFA engine and portions of rules are assigned to the NFA engine. Fragments matched by the DFA engine may be sorted by a sorter into NFA launch positions before activating NFA states. A dynamically reconfigurable NFA cell array may be used. An NFA state signaled by a DFA…
Receiver with Parallel Decision Feedback Equalizers
Granted: May 29, 2014
Application Number:
20140146867
Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M…
TRANSCEIVER WITH SHORT-CIRCUIT DETECTION AND PROTECTION
Granted: May 29, 2014
Application Number:
20140146860
A USB transceiver has transmitter circuitry, receiver circuitry, short-circuit detection circuitry, and short-circuit protection circuitry. The transmitter circuitry transmits a differential pair of outgoing data signals to a cable connected to the transceiver, and the receiver circuitry receives the differential pair of outgoing data signals via bi-directional input-output pins. The short-circuit detection circuitry analyzes each of the outgoing differential data signals to detect a…
Systems and Methods for Enhanced Servo Data Processing
Granted: May 29, 2014
Application Number:
20140146413
Systems and method relating generally to detecting information, and more particularly without limitation to systems and methods for synchronizing to a data stream.
