Low Density Parity Check Decoder With Flexible Saturation
Granted: May 22, 2014
Application Number:
20140143628
Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values.
SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN INTEGRATED CIRCUIT
Granted: May 22, 2014
Application Number:
20140143621
An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells, and the associated control circuitry is coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit. The scan test circuitry is configurable by the control…
Self-Sizing Dynamic Cache for Virtualized Environments
Granted: May 22, 2014
Application Number:
20140143496
A method and system for self-sizing dynamic cache for virtualized environments is disclosed. The preferred embodiment self sizes unequal portions of the total amount of cache and allocates to a plurality of active virtualized machines (VM) according to VM requirements and administrative standards. As a new VM may emerge and request an amount of cache, the cache controller reclaims currently used cache from the active VM and reallocates the unequal portions of cache required by each VM.…
Constrained System Endec
Granted: May 22, 2014
Application Number:
20140143289
Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data for constrained systems with reduced or eliminated need for hardware and time intensive arithmetic operations such as multiplication and division.
COMPLEX NFA STATE MATCHING
Granted: May 22, 2014
Application Number:
20140143195
Disclosed is a method and system for matching a complex NFA state comprising a spinner followed by a character class sequence which may be represented by the general regular expression form [S] {N,M}[A0][A1] . . . [Ak?1]. An input transition activates the spinner and the spin count increments with successive matches of the spin class [S]. When the spin count is between N and M, sequence matching begins. Several base sequence CCLs are compared in parallel with a corresponding window of…
Harmonic Ratio Based Defect Classifier
Granted: May 22, 2014
Application Number:
20140140182
The disclosure is directed to a system and method for detecting and classifying at least one media defect. A periodic pattern is written to a medium to yield at least one waveform. The magnitude of the waveform is compared against a defect threshold to detect the presence or absence of media defects in the medium. When at least one defect is detected, a magnitude for each of at least two harmonics of the waveform is determined in the defect range. The defect is classified by comparing a…
READ CHANNEL ERROR CORRECTION USING MULTIPLE CALIBRATORS
Granted: May 22, 2014
Application Number:
20140139943
Read channel circuitry comprises a decoder and error correction circuitry. The error correction circuitry is configured to calibrate a first set of filters using a read channel data signal, to determine first hard decision information regarding the read channel data signal using the calibrated first set of filters, to determine an error corrected read channel data signal using the first hard decision information, to calibrate a second set of filters using the error corrected read channel…
ADAPTIVE SERVO ADDRESS MARK DETECTION
Granted: May 22, 2014
Application Number:
20140139939
Various embodiments of the present inventions provide systems and methods for adaptive servo address mark detection.
DEPTH IMAGING METHOD AND APPARATUS WITH ADAPTIVE ILLUMINATION OF AN OBJECT OF INTEREST
Granted: May 22, 2014
Application Number:
20140139632
A depth imager such as a time of flight camera or a structured light camera is configured to capture a first frame of a scene using illumination of a first type, to define a first area associated with an object of interest in the first frame, to identify a second area to be adaptively illuminated based on expected movement of the object of interest, to capture a second frame of the scene with adaptive illumination of the second area using illumination of a second type different than the…
CIRCUIT NOISE EXTRACTION USING FORCED INPUT NOISE WAVEFORM
Granted: May 15, 2014
Application Number:
20140137063
Techniques for use in integrated circuit design systems for extracting noise threshold data for selected cells. For example, a method comprises the following steps. A cell is selected from one or more cells in a given collection of standardized cells. Each of the one or more cells represents one or more functional circuit design blocks that are usable as part of a design of an integrated circuit. A noise signal is generated or selected. The noise signal is applied to an input node of the…
ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE
Granted: May 15, 2014
Application Number:
20140136927
Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and…
READ DISTURB HANDLING FOR NON-VOLATILE SOLID STATE MEDIA
Granted: May 15, 2014
Application Number:
20140136884
Described embodiments track a read disturb limit of a solid-state media coupled to a media controller. The media controller receives a read operation from a host device. In response to the received read operation, the media controller determines one or more associated regions of the solid-state media accessed by the read operation and reads the associated regions to provide read data to the host device. Based on a probability value corresponding to each of the associated regions, the…
READ DISTURB EFFECT DETERMINATION
Granted: May 15, 2014
Application Number:
20140136883
An apparatus comprising a non-volatile memory and a controller. The controller is coupled to the non-volatile memory and configured to (i) accumulate a read disturb count for a first region of the non-volatile memory, (ii) accumulate error statistics for a second region of the non-volatile memory, (iii) determine, based upon both the read disturb count and the error statistics, whether the first region has reached a read disturb limit, and (iv) in response to determining that the first…
METHODS AND APPARATUS FOR FAST CONTEXT SWITCHING OF SERIAL ADVANCED TECHNOLOGY ATTACHMENT IN ENHANCED SERIAL ATTACHED SCSI EXPANDERS
Granted: May 15, 2014
Application Number:
20140136739
Methods and apparatus for enabling Fast Context Switching (FCS) operation of an enhanced Serial Attached SCSI (SAS) expander and initiator for switching between one or more concurrently established connections including at least one Serial Advanced Technology Attachment (SATA) target device connection. Features and aspects hereof provide for enhanced logic within a SAS expander and/or initiator to detect the completion of an exchange over a first connection between an initiator device…
IMPULSE REGULAR EXPRESSION MATCHING
Granted: May 15, 2014
Application Number:
20140136465
Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.
APPARATUS AND METHOD FOR SENSING TRANSISTOR AGING EFFECTS
Granted: May 15, 2014
Application Number:
20140136128
An integrated circuit implements a transistor aging effects sensor comprising first and second delay lines, each comprising a plurality of delay elements, and a register. The register comprises a plurality of flip-flops having data inputs driven by respective outputs of respective ones of the delay elements of the first delay line and clock inputs driven by one or more clock signals provided by at least one of the delay elements of the second delay line. Data outputs of the flip-flops of…
LOSS OF LOCK DETECTOR FOR CLOCK AND DATA RECOVERY SYSTEM
Granted: May 15, 2014
Application Number:
20140132320
An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests…
APPARATUS AND METHOD FOR SENSING TRANSISTOR MISMATCH
Granted: May 15, 2014
Application Number:
20140132303
An integrated circuit implements a transistor mismatch sensor comprising first and second inverter chains coupled to a register. The register comprises a plurality of flip-flops having clock inputs driven by an output of the first inverter chain and data inputs driven by an output of the second inverter chain. Data outputs of the flip-flops of the register are indicative of an amount of mismatch between transistors of different conductivity types in the first and second inverter chains.…
MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS
Granted: May 15, 2014
Application Number:
20140131854
One aspect provides an integrated circuit (IC) multi-chip packaging assembly, comprising a first IC chip having packaging substrate contacts and bridging block contacts, a second IC chip having packaging substrate contacts and bridging block contacts, and a bridging block partially overlapping the first and second IC chips and having interconnected electrical contacts on opposing ends thereof that contact the bridging block contacts of the first IC chip and the second IC chip to thereby…
Systems and Methods for Partially Conditioned Noise Predictive Equalization
Granted: May 8, 2014
Application Number:
20140129603
Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a…
