CIRCUIT AND METHOD FOR DYNAMICALLY CHANGING A TRIP POINT IN A SENSING INVERTER
Granted: May 8, 2014
Application Number:
20140126316
A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit…
Techniques For Secure Storage Hijacking Protection
Granted: May 8, 2014
Application Number:
20140130188
A hijack-protected, secure storage device requires proof that the user has actual physical access to the device before protected commands are executed. Examples of protected commands include attempts to change storage device security credentials of the device, erasure of protected portions of the device, and attempts to format, sanitize, and trim the device. Various techniques for proving the actual physical possession include manipulating a magnet to control a magnetic reed switch…
System and Method for Check-Node Unit Message Processing
Granted: May 8, 2014
Application Number:
20140130061
The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a…
STRUCTURAL RULE ANALYSIS WITH TCL SCRIPTS IN SYNTHESIS OR STA TOOLS AND INTEGRATED CIRCUIT DESIGN TOOLS
Granted: May 8, 2014
Application Number:
20140130000
A method of designing a circuit, an apparatus and a structural analysis tool are disclosed. In one embodiment, the structural analysis tool includes: (1) a structural analyzer configured to apply a structural rule to the circuit design in a design environment of said design process having valid timing data and (2) a structural assessor configured to generate structural data of the circuit design based on application of the structural rule by the structural analyzer.
HIERARCHICAL EQUIVALENCE CHECKING AND EFFICIENT HANDLING OF EQUIVALENCE CHECKS WHEN ENGINEERING CHANGE ORDERS ARE IN AN UNSHARABLE REGISTER TRANSFER LEVEL
Granted: May 8, 2014
Application Number:
20140129998
An apparatus, a hierarchical method of equivalence checking a circuit design and equivalency checking after engineering change orders in a circuit design are disclosed herein. In one embodiment, a method of equivalence checking includes: (1) receiving a post-engineering change order (ECO) netlist of a first one of the functional blocks, wherein the post-ECO netlist has been verified employing an equivalence checker, (2) generating a top level netlist for the circuit design including the…
Flexible Low Density Parity Check Code Seed
Granted: May 8, 2014
Application Number:
20140129905
Various embodiments of the present inventions provide systems and methods for data processing with a flexible LDPC seed.
Test Pattern Optimization for LDPC Based Flawscan
Granted: May 8, 2014
Application Number:
20140129890
A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length…
System and Method for Booting Multiple Servers from Snapshots of an Operating System Installation Image
Granted: May 8, 2014
Application Number:
20140129816
The disclosure is directed to a system and method for booting a plurality of servers from at least one of a primary storage drive and a secondary storage drive. An operating system installation image is stored in a primary storage drive. Snapshots including modifications to the operating system installation image are stored in a plurality of partitions of a secondary storage device. A lookup table directs servers to read unmodified portions of the operating system installation image from…
CACHE PREFETCH FOR NFA INSTRUCTIONS
Granted: May 8, 2014
Application Number:
20140129775
Disclosed is a method of pre-fetching NFA instructions to an NFA cell array. The method and system fetch instructions for use in an L1 cache during NFA instruction execution. Successive instructions from a current active state are fetched and loaded in the L1 cache. Disclosed is a system comprising an external memory, a cache line fetcher, and an L1 cache where the L1 cache is accessible and searchable by an NFA cell array and where successive instructions from a current active state in…
Systems and Methods for Partially Conditioned Noise Predictive Equalization
Granted: May 8, 2014
Application Number:
20140129603
Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a…
CIRCUIT AND METHOD FOR IMPROVING SENSE AMPLIFIER REACTION TIME IN MEMORY READ OPERATIONS
Granted: May 8, 2014
Application Number:
20140126315
A sense amplifier circuit, a method of modifying a differential voltage in a sense amplifier circuit and a memory system incorporating the sense amplifier circuit or the method. In one embodiment, the sense amplifier circuit includes: (1) a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read and (2) a sense speed…
HIGH-VOLTAGE TOLERANT BIASING ARRANGEMENT USING LOW-VOLTAGE DEVICES
Granted: May 8, 2014
Application Number:
20140125404
A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias…
THERMAL IMPROVEMENT OF INTEGRATED CIRCUIT PACKAGES
Granted: May 8, 2014
Application Number:
20140124918
An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.
Single-Ended Sense Amplifier for Solid-State Memories
Granted: May 1, 2014
Application Number:
20140119093
Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an…
METHODS AND STRUCTURE FOR SERIAL ATTACHED SCSI EXPANDERS THAT SELF-CONFIGURE ROUTING ATTRIBUTES OF THEIR PORTS
Granted: May 1, 2014
Application Number:
20140122761
Methods and structure are provided for Serial Attached SCSI (SAS) expanders that program their own routing attributes. The structure includes a SAS expander comprising multiple physical links with associated transceivers (PHYs), wherein the PHYs are configured into ports at the expander, and a memory that defines routing attributes for each of the ports. The SAS expander also comprises a control unit that is operable to detect a discovery Serial Management Protocol (SMP) request received…
METHOD OF CONCEALING PICTURE HEADER ERRORS IN DIGITAL VIDEO DECODING
Granted: May 1, 2014
Application Number:
20140119445
A method of concealing errors in picture header information within H.263-encoded video compares current group-of-block frame identification (GFID) information to GFID information from the previous frame. If the GFID values are equal, the picture header information from the previous frame is used to decode the current frame. Otherwise, a selected parameter in the previous picture header information (for example, “picture type”) is altered and decoding proceeds with the altered picture…
Method and Apparatus for High Density Pulse Density Modulation
Granted: May 1, 2014
Application Number:
20140119427
A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can…
INTERFACE FOR ASYNCHRONOUS VIRTUAL CONTAINER CHANNELS AND HIGH DATA RATE PORT
Granted: May 1, 2014
Application Number:
20140119389
Data rate justification circuitry adapted to control one or more communications between a physical layer device and a link layer device. In a first direction of communication, the data rate justification circuitry is configured to receive first virtual container data from the physical layer device over two or more asynchronous virtual container channels, and to synchronize the first virtual container data and aggregate the first virtual container data for transmission to the link layer…
Laser Power Control in a Heat-Assisted Magnetic Recording System
Granted: May 1, 2014
Application Number:
20140119164
A heat-assisted magnetic recording system may include, but is not limited to: at least one magnetic recording read/write head; at least one laser diode configured to illuminate at least a portion of at least one magnetic recording medium; at least one laser power level sensor configured to detect a power level of the at least one laser diode; and a controller configured to modify one or more power level settings associated with the at least one laser diode in response to one or more…
SEGMENTED MEMORY HAVING POWER-SAVING MODE
Granted: May 1, 2014
Application Number:
20140119147
A memory array is divided into multiple segments, each segment having one or more rows of bitcells. Each segment has control circuitry that controls whether the segment is in an active mode or a power-saving, sleep mode. The control circuitry ensures that a segment transitions from sleep mode to active mode before a row of the segment is accessed by driving a corresponding wordline high. The control circuitry also ensures that, at the end of a row access, the wordline is driven low…
