METHOD OF CONCEALING PICTURE HEADER ERRORS IN DIGITAL VIDEO DECODING
Granted: May 1, 2014
Application Number:
20140119445
A method of concealing errors in picture header information within H.263-encoded video compares current group-of-block frame identification (GFID) information to GFID information from the previous frame. If the GFID values are equal, the picture header information from the previous frame is used to decode the current frame. Otherwise, a selected parameter in the previous picture header information (for example, “picture type”) is altered and decoding proceeds with the altered picture…
Hardware Architecture and Implementation of Low Power Layered Multi-Level LDPC Decoder
Granted: May 1, 2014
Application Number:
20140122979
A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.
LEH Memory Module Architecture Design in the Multi-Level LDPC Coded Iterative System
Granted: May 1, 2014
Application Number:
20140122971
A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.
Sector Failure Prediction Method and Related System
Granted: May 1, 2014
Application Number:
20140122923
A method and system is disclosed for identification and removal of a memory sector prone to failure. The method performs satisfaction checks on the memory sector and monitors and stores returned Unsatisfied Checks (USC) for analysis by a pattern recognition algorithm. Once a first global iteration is pattern matched with a second global iteration from the sector, the method determines the period of the repetitive pattern. The method then identifies, as the sector prone to failure, the…
METHODS AND STRUCTURE TO ASSURE DATA INTEGRITY IN A STORAGE DEVICE CACHE IN THE PRESENCE OF INTERMITTENT FAILURES OF CACHE MEMORY SUBSYSTEM
Granted: May 1, 2014
Application Number:
20140122922
Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training,…
METHODS AND STRUCTURE ESTABLISHING NESTED REDUNDANT ARRAY OF INDEPENDENT DISKS VOLUMES WITH AN EXPANDER
Granted: May 1, 2014
Application Number:
20140122798
Methods and structure are provided for provisioning a Redundant Array of Independent Disks (RAID) volume via an expander that can be used to provision a RAID volume managed by an external RAID controller. The structure includes a Serial Attached SCSI (SAS) expander. The expander comprises physical links with transceivers (PHYs) that directly couple with storage devices, a protocol target and a control unit. The control unit provisions a first RAID volume with multiple storage devices…
METHOD AND STRUCTURES FOR PERFORMING A MIGRATION OF A LOGICAL VOLUME WITH A SERIAL ATTACHED SCSI EXPANDER
Granted: May 1, 2014
Application Number:
20140122797
Methods and structure for migrating a logical volume with a Serial Attached SCSI (SAS) expander are provided. The expander comprises a plurality of physical links with associated transceivers (PHYs). The expander further comprises a control unit operable to select a logical volume, and to initiate migration of data from the selected logical volume to a backup logical volume. Further, the expander includes a Serial SCSI Protocol (SSP) target of the expander operable to intercept commands…
METHODS AND STRUCTURE FOR MANAGING PROTECTION INFORMATION WITH A SERIAL ATTACHED SCSI EXPANDER
Granted: May 1, 2014
Application Number:
20140122745
Methods and structure are provided for managing Protection Information (PI) in a Serial Attached SCSI (SAS) expander. The Serial Attached SCSI (SAS) expander comprises a Serial Management Protocol (SMP) target. The SMP target is operable to receive, from a Redundant Array of Inexpensive Disks (RAID) controller, an SMP command for managing Protection Information (PI) for a RAID volume at the SAS expander. The expander further comprises a control unit operable to generate PI for the RAID…
METHODS AND STRUCTURE FOR PERFORMING A REBUILD OF A LOGICAL VOLUME WITH A SERIAL ATTACHED SCSI EXPANDER
Granted: May 1, 2014
Application Number:
20140122744
Methods and structure are provided for performing a rebuild using a Serial Attached SCSI (SAS) expander. The SAS expander includes an SMP target operable to receive, from a Redundant Array of Inexpensive Disks (RAID) controller, a Serial Management Protocol (SMP) command for initiating a rebuild of a RAID volume at the SAS expander. The SAS expander also includes a control unit operable to initiate a rebuild of the RAID volume based on the received SMP command from the controller, and a…
Digital Radio Frequency Clocking Methods
Granted: May 1, 2014
Application Number:
20140119470
A method and system for synchronous transfer of bitstream data between a power-driver chip and a digital signal processing chip in a digital radio frequency transmit system is disclosed. A master phase-locked-loop located in the power-driver chip is utilized to provide master clocking control for the digital radio frequency transmit system. Furthermore, the clocking method and system is configurable to secure precise carrier frequency positioning of a digitally-generated radio frequency…
Method and Apparatus for High Density Pulse Density Modulation
Granted: May 1, 2014
Application Number:
20140119427
A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can…
INTERFACE FOR ASYNCHRONOUS VIRTUAL CONTAINER CHANNELS AND HIGH DATA RATE PORT
Granted: May 1, 2014
Application Number:
20140119389
Data rate justification circuitry adapted to control one or more communications between a physical layer device and a link layer device. In a first direction of communication, the data rate justification circuitry is configured to receive first virtual container data from the physical layer device over two or more asynchronous virtual container channels, and to synchronize the first virtual container data and aggregate the first virtual container data for transmission to the link layer…
APPARATUS, METHOD AND SYSTEM FOR CANCELLING AN INPUT-REFERRED OFFSET IN A PIPELINE ADC
Granted: April 24, 2014
Application Number:
20140111361
An apparatus, method and system for offset compensation in a pipeline analog-to-digital converter. A group of capacitors includes one or more sampling capacitors and one or more feedback capacitors, wherein an input to the pipeline analog-to-digital converter circuit is connected to group of capacitors. An amplifier includes a non-inverting input terminal connected to a ground and an inverting input connected to the group of capacitors. The sampling and feedback capacitors are both…
Systems and Methods for Positive Feedback Short Media Defect Detection
Granted: April 24, 2014
Application Number:
20140115431
Various systems and methods for media defect detection.
METHOD AND SYSTEM TO REDUCE SYSTEM BOOT LOADER DOWNLOAD TIME FOR SPI BASED FLASH MEMORIES
Granted: April 24, 2014
Application Number:
20140115229
Method and system for providing increased frequency of flash memories compatible to Serial Peripheral Interface (SPI) bus protocol by delayed data capturing so that system boot loader down load time reduces for a given memory configuration. Methods and systems are provided for operating the memory at the device rated frequency.
NFA CHARACTER CLASS MATCHING
Granted: April 24, 2014
Application Number:
20140114996
Disclosed is method of matching a character class to a symbol of an input stream. A character class, or a plurality of character classes, is defined into an accessible format which when accessed is compared to a symbol in an input stream. The format may be stored in an NFA array cell or it may be broadcast to the cell array with an input symbol for comparison.
METHOD TO SHORTEN HASH CHAINS IN LEMPEL-ZIV COMPRESSION OF DATA WITH REPETITIVE SYMBOLS
Granted: April 24, 2014
Application Number:
20140114937
An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a sequence of hash values in a table from a stream of data values with repetitive values, (ii) find two consecutive ones of the hash values in the sequence that have a common value and (iii) create a shortened hash chain by generating a pointer in the table at an intermediate location that corresponds to a second of the two consecutive hash values. The pointer generally points forward in the table…
METHOD AND SYSTEM FOR AN ADAPTIVE NEGATIVE-BOOST WRITE ASSIST CIRCUIT FOR MEMORY ARCHITECTURES
Granted: April 24, 2014
Application Number:
20140112062
Disclosed is an adaptive negative bit-line boost write assist technique in which coupling capacitance scales with the number of rows and thereby maintains a constant negative bit-line level. The change in the coupling capacitance in neighboring signals as the height increases is utilized. The change is utilized for negative bit-line voltage generation.
MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL
Granted: April 24, 2014
Application Number:
20140111880
A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a…
OPTICAL SOURCE DRIVER CIRCUIT FOR DEPTH IMAGER
Granted: April 24, 2014
Application Number:
20140111617
A depth imager such as a time of flight camera comprises a driver circuit and an optical source. The driver circuit comprises a frequency control module and a controllable oscillator having a control input coupled to an output of the frequency control module. An output of the controllable oscillator is coupled to an input of the optical source, and a driver signal provided by the driver circuit to the optical source utilizing the controllable oscillator varies in frequency under control…
