Systems and Methods for Positive Feedback Short Media Defect Detection
Granted: April 24, 2014
Application Number:
20140115431
Various systems and methods for media defect detection.
Systems and Methods for Iterative Data Processing Using Negative Feedback Iteration
Granted: April 24, 2014
Application Number:
20140115430
Systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing.
METHODS AND APPARATUS FOR ZONE GROUP IDENTIFIER REPLACEMENT IN FAST CONTEXT SWITCHING ENHANCED SERIAL ATTACHED SCSI EXPANDERS
Granted: April 24, 2014
Application Number:
20140115418
Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.
Systems and Methods for Short Media Defect Detection Using Multi-Iteration Soft Data Feedback
Granted: April 24, 2014
Application Number:
20140115407
Various systems and methods for media defect detection.
CHILD STATE PRE-FETCH IN NFAs
Granted: April 24, 2014
Application Number:
20140115263
Disclosed is a method and apparatus for pre-fetching child states in an NFA cell array. A pre-fetch depth value is determined for each transition in an NFA graph. The pre-fetch depth value is accessed for transition from an active state in the NFA graph. The child states of the active state are pre-fetched to the depth of the pre-fetch depth value recursively. A loader loads the pre-fetched states into the NFA cell array.
VECTOR PROCESSOR HAVING INSTRUCTION SET WITH VECTOR CONVOLUTION FUNCTION FOR FIR FILTERING
Granted: April 17, 2014
Application Number:
20140108477
A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector…
Systems and Methods for Enhanced Local Iteration Randomization in a Data Decoder
Granted: April 17, 2014
Application Number:
20140108880
systems and methods for data processing particularly related local iteration randomization in a data decoding circuit.
Systems and Methods for Indirect Information Assisted Media Defect Scan
Granted: April 17, 2014
Application Number:
20140108875
Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for media defect detection.
Heuristic Approach for Faster Consistency Check in a Redundant Storage System
Granted: April 17, 2014
Application Number:
20140108855
A method for reducing an amount of time required for performing consistency checking in a redundant storage system includes steps of: providing an information repository associated with each of a primary drive and at least one redundant drive; storing, in the information repository, information relating to input/output failures on the primary drive and redundant drive; determining a likelihood that one or more regions of the primary drive and/or redundant drive contains inconsistent data…
Scalable Data Structures for Control and Management of Non-Volatile Storage
Granted: April 17, 2014
Application Number:
20140108703
Scalable control/management data structures enable optimizing performance and/or attempting to achieve a particular performance target of an SSD in accordance with host interfacing, number of NVM devices, NVM characteristics and size, and NVM aging and performance decline. Pre-scaled data structures are included in SSD controller firmware loadable at system initialization. Static data structure configurations enable load-once-operate-for-product-lifetime operation for consumer…
ADAPTIVE MAXIMUM A POSTERIORI (MAP) DETECTOR IN READ CHANNEL
Granted: April 17, 2014
Application Number:
20140105266
An adaptive detector, such as a maximum a posteriori (MAP) detector for a read channel, is disclosed. In one or more embodiments, a data processing apparatus, such as a read channel digital front end, includes an equalizer configured to equalize X sample data to yield equalized Y sample data. A noise predictive filter configured to receive the equalized Y sample data yielded by the equalizer is operable to filter noise in the equalized Y sample data. A detector is configured to perform…
ACCELERATED SOFT READ FOR MULTI-LEVEL CELL NONVOLATILE MEMORIES
Granted: April 17, 2014
Application Number:
20140104943
A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. For example, the given accelerated…
ENHANCED QUALITY-SORTING SCHEDULER
Granted: April 17, 2014
Application Number:
20140104720
Aspects of the disclosure pertain to a read channel system and method for providing sector prioritization for promoting improved sector processing performance. The system and method, during processing of sectors of data, prioritize each of the sectors for further processing based upon: a global iteration index of each sector, trapping set characteristics of each sector and processing latency of each sector.
DATA RECOVERY USING NO SYNC MARK RETRY
Granted: April 17, 2014
Application Number:
20140104719
A read channel is configured to receive at least part of a data fragment read from a storage media into a register, wherein the data fragment is configured to be formatted with a preamble, a sync mark (e.g., a syncMark), and user data, and wherein the data fragment is missing a sync mark. A position in the data fragment is selected, a sync mark is assumed at the selected position. The data is then processed assuming the sync mark is at the selected position of the data fragment to…
ZERO GAIN START AND GAIN ACQUISITION BASED ON ADAPTIVE ANALOG-TO-DIGITAL CONVERTER TARGET
Granted: April 17, 2014
Application Number:
20140104717
Aspects of the disclosure pertain to a system and method for providing zero gain start (ZGS) and gain acquisition based on an adaptive analog-to-digital converter (ADC) target. The adaptive ADC target is used to collect channel characteristics and based on the adaptive ADC target, an adjusted 2T amplitude target value is generated.
PREAMPLIFIER-TO-CHANNEL COMMUNICATION IN A STORAGE DEVICE
Granted: April 17, 2014
Application Number:
20140104716
An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a…
OPTIMIZING COMPRESSION ENGINE THROUGHPUT VIA RUN PRE-PROCESSING
Granted: April 17, 2014
Application Number:
20140104085
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a reduced representation of an input sequence of characters by replacing a repetition of a sequence of one or more characters by a code representing the repetition of the sequence of one or more characters. The second circuit may be configured to generate a compressed representation of the input sequence of characters in response to the reduced representation of the input sequence…
OPTIMIZED BITSTREAM ENCODING FOR COMPRESSION
Granted: April 17, 2014
Application Number:
20140104084
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate (i) a compressed representation of an input sequence of characters and (ii) statistics regarding one or more types of information in the compressed representation of the input sequence of characters. The second circuit may be configured to generate a compressed bitstream representation of the input sequence of characters in response to the compressed representation of the input…
BOUNDED BIAS CIRCUIT WITH EFFICIENT VT-TRACKING FOR HIGH VOLTAGE SUPPLY/LOW VOLTAGE DEVICE
Granted: April 17, 2014
Application Number:
20140103991
Disclosed is a device and method for providing a bounded bias voltage with improved Process Voltage Temperature (PVT) adjustment. An embodiment may include a bias_n generation circuit that adjusts a bias_n voltage for PVT as a function of two bias_n NMOS transistors/diodes and a bias_p generation circuit that adjusts a bias_p voltage for PVT as a function of two bias_p PMOS transistors/diodes. An embodiment may further include a PVT adjusted bounded bias voltage circuit comprised of a…
JOINT TRANSMITTER AND RECEIVER GAIN OPTIMIZATION FOR HIGH-SPEED SERIAL DATA SYSTEMS
Granted: April 10, 2014
Application Number:
20140098844
Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed…
