JOINT TRANSMITTER AND RECEIVER GAIN OPTIMIZATION FOR HIGH-SPEED SERIAL DATA SYSTEMS
Granted: April 10, 2014
Application Number:
20140098844
Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed…
Low Density Parity Check Layer Decoder For Codes With Overlapped Circulants
Granted: April 10, 2014
Application Number:
20140101510
The present inventions are related to systems and methods for decoding data in an LDPC layer decoder for LDPC codes with overlapped circulants.
Systems and Methods for Parallel Retry Processing During Iterative Data Processing
Granted: April 10, 2014
Application Number:
20140101509
Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
SCAN TEST CIRCUITRY CONFIGURED TO PREVENT VIOLATION OF MULTIPLEXER SELECT SIGNAL CONSTRAINTS DURING SCAN TESTING
Granted: April 10, 2014
Application Number:
20140101501
An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured…
CIRCUITS AND METHODS FOR FUNCTIONAL TESTING OF INTEGRATED CIRCUIT CHIPS
Granted: April 10, 2014
Application Number:
20140101500
Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The scan test circuitry includes scan chains with scan cells interspersed throughout the core circuitry. The scan control circuitry controls the scan test circuitry to scan test the core circuitry. The debug control circuitry utilizes the scan test circuitry and controls the scan control circuitry…
Systems and Methods for Modified Quality Based Priority Scheduling During Iterative Data Processing
Granted: April 10, 2014
Application Number:
20140101483
Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
COMMON HOT SPARE FOR MULTIPLE RAID GROUPS
Granted: April 10, 2014
Application Number:
20140101480
A storage system assigns one or more large disks in a storage enclosure as a common dedicated hot spare that is used by multiple RAID groups. Storage space equivalent to the smallest physical disk in a RAID group is allocated on the common dedicated hot spare. A mapping of this allocated storage space to the RAID group is maintained in nonvolatile memory. When a disk fails in the RAID group, the allocated storage space on the common dedicated hot spare receives a rebuild of the failed…
Variable Over-Provisioning For Non-Volatile Storage
Granted: April 10, 2014
Application Number:
20140101379
Dynamically varying Over-Provisioning (OP) enables improvements in lifetime, reliability, and/or performance of a Solid-State Disk (SSD) and/or a flash memory therein. A host coupled to the SSD writes newer data to the SSD. If the newer host data is less random than older host data, then entropy of host data on the SSD decreases. In response, an SSD controller of the SSD dynamically alters allocations of the flash memory, decreasing host allocation and increasing OP allocation. If the…
START POINTER TRACKING IN NFAs
Granted: April 10, 2014
Application Number:
20140101185
In a hardware engine, finding rule matches within an input stream by executing a Nondeterministic Finite Automaton (NFA) with active states tracked in parallel cells, a Start Pointer (SP) is captured by the cell beginning a match and passed from cell to cell until the match completes, when it is reported by the cell ending the match. For multiple overlapping matches, different cells may hold different SPs, and a cell representing multiple NFA states may hold multiple SPs. Methods are…
BLENDED MATCH MODE DFA SCANNING
Granted: April 10, 2014
Application Number:
20140101176
Disclosed is a method for simultaneously finding matches for rules that require greedy matching and comprehensive matching by executing a single Deterministic Finite Automaton (DFA). DFAs annotations are used to enable a single DFA to represent rules that require greedy and comprehensive matching. DFA descents are performed from various positions in an input stream, match information is recorded and match results are selectively generated (filtered) to achieve the greedy or comprehensive…
SEMICONDUCTOR STRUCTURE WITH WAVEGUIDE
Granted: April 3, 2014
Application Number:
20140092621
A light-emitting diode (LED) apparatus comprises a substrate, a first layer formed over at least a portion of the substrate, an active layer formed over at least a portion of the first layer, a second layer formed over at least a portion of the active layer, and at least one waveguide formed below the substrate. A first portion of light from the LED is directed in a first direction and a second portion of light from the LED is directed in a second direction via the waveguide, the second…
USING ENTIRE AREA OF CHIP IN TDDB CHECKING
Granted: April 3, 2014
Application Number:
20140096098
A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.
BREAKING UP LONG-CHANNEL FIELD EFFECT TRANSISTOR INTO SMALLER SEGMENTS FOR RELIABILITY MODELING
Granted: April 3, 2014
Application Number:
20140096094
A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is…
BIAS-TEMPERATURE INSTABILITY RELIABILITY CHECKS BASED ON GATE VOLTAGE THRESHOLD FOR RECOVERY
Granted: April 3, 2014
Application Number:
20140095140
A method of determining a saturation current degradation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation with gate voltage (Vgs) at a level that causes Idsat degradation by bias temperature instability (BTI). A second dependence of the saturation current (Idsat) recovery versus gate voltage (Vgs) is also measured for the MOS integrated circuit fabrication process. A recovery voltage threshold value…
HOT-CARRIER INJECTION RELIABILITY CHECKS BASED ON BACK BIAS EFFECT ON THRESHOLD VOLTAGE
Granted: April 3, 2014
Application Number:
20140095139
A method for checking for reliability problems that includes simulating a circuit having at least one MOS transistor. The circuit includes at least a first MOS transistor. Based on the results of the simulation of the circuit, a bulk-to-source voltage (Vbs) is calculated for the first MOS transistor. Based on the calculated Vbs for the first MOS transistor, a threshold voltage (Vth) for the first MOS transistor is calculated. Based on the Vth, an effective Vgs for the first MOS…
CHECKING FOR HIGH BACK-BIAS IN LONG GATE-LENGTH, HIGH TEMPERATURE CASES
Granted: April 3, 2014
Application Number:
20140095138
A method for checking for reliability problems includes simulating a circuit having at least one MOS transistor that includes a first MOS transistor. Based on the results of this simulation of the circuit, a gate-to-bulk voltage (Vgb) for the first MOS transistor is calculated. A voltage limit based on the length of the channel of the first MOS transistor is selected. If Vgb is greater than the voltage limit, a warning message is generated.
HOT-CARRIER INJECTION RELIABILITY CHECKS BASED ON BIAS TEMPERATURE INSTABILITY - HOT CARRIER INJECTION INTERACTION
Granted: April 3, 2014
Application Number:
20140095127
A method of adjusting an expected lifetime equation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation versus gate voltage (Vgs). This first dependence is indicative of Idsat degradation at least partially caused by hot carrier injection (HCI). A second dependence of the saturation current (Idsat) degradation versus gate voltage (Vgs) is also measured. This second dependence is indicative of Idsat…
HOT-CARRIER INJECTION RELIABILITY CHECKS BASED ON GATE VOLTAGE DEPENDENCY
Granted: April 3, 2014
Application Number:
20140095126
A method for checking for reliability problems includes measuring, for a MOS integrated circuit fabrication process, a dependence of a saturation current (Idsat) degradation versus gate voltage (Vgs). The saturation current (Idsat) degradation versus drain voltage (Vds) is also measured for the MOS integrated circuit process. The measured data points of an amount of time until a threshold degradation occurs versus Vgs divided by Vds is fitted to a curve in order to determine a first…
FLASH CHANNEL PARAMETER MANAGEMENT WITH READ SCRUB
Granted: April 3, 2014
Application Number:
20140095110
An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the…
METHOD AND SYSTEM FOR INTELLIGENT DEEP PACKET BUFFERING
Granted: April 3, 2014
Application Number:
20140092914
Disclosed is a method and system for deep packet buffering on a switch core comprising an ingress and egress deep packet buffer and an external deep packet buffer.
