USING ENTIRE AREA OF CHIP IN TDDB CHECKING
Granted: April 3, 2014
Application Number:
20140096098
A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.
CORE WRAPPING IN THE PRESENCE OF AN EMBEDDED WRAPPED CORE
Granted: April 3, 2014
Application Number:
20140096097
An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.
BREAKING UP LONG-CHANNEL FIELD EFFECT TRANSISTOR INTO SMALLER SEGMENTS FOR RELIABILITY MODELING
Granted: April 3, 2014
Application Number:
20140096094
A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is…
PATTERN-DEPENDENT SHORT MEDIA DEFECT DETECTION
Granted: April 3, 2014
Application Number:
20140095963
Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector.
LAYERED DECODER ENHANCEMENT FOR RETAINED SECTOR REPROCESSING
Granted: April 3, 2014
Application Number:
20140095961
A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (HDD) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors. A memory is coupled with the processor and configured to retain data received from one or more of the sectors, e.g., in retained sector reprocessing (RSR) embodiments. The system is configured to update messages in…
Back-Off Retry with Priority Routing
Granted: April 3, 2014
Application Number:
20140095754
A method for back-off retry with priority routing includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the SAS expander via at least one inter-expander link (IEL), the expander including a first SAS expander and at least one additional SAS expander. The method includes routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS…
LDPC Decoder With Fractional Local Iterations
Granted: March 27, 2014
Application Number:
20140089757
The present inventions are related to systems and methods for an LDPC decoder with fractional local iterations that may be used in a data processing system with an LDPC decoder and data detector to better balance processing times in the LDPC decoder and data detector.
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion
Granted: March 27, 2014
Application Number:
20140089881
Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second…
CONTENT ADDRESSABLE MEMORY CONTINUOUS ERROR DETECTION WITH INTERLEAVE PARITY
Granted: March 27, 2014
Application Number:
20140089769
Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare…
METHOD AND SYSTEM FOR GENERATION OF A TIE-BREAKING METRIC IN A LOW-DENSITY PARITY CHECK DATA ENCODING SYSTEM
Granted: March 27, 2014
Application Number:
20140089767
The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the…
DYNAMIC REDUNDANCY MAPPING OF CACHE DATA IN FLASH-BASED CACHING SYSTEMS
Granted: March 27, 2014
Application Number:
20140089558
A method for managing redundancy of data in a solid-state cache system including at least three solid-state storage modules. The method may include designating one or more extents of each dirty mirror pair to be of a particular priority order of at least two priority orders. The at least two priority orders can include at least a highest priority order. The highest priority order can have a higher relative priority than the other priority orders. The method may also include performing at…
LEASED LOCK IN ACTIVE-ACTIVE HIGH AVAILABILITY DAS SYSTEMS
Granted: March 27, 2014
Application Number:
20140089545
A method and system for IO processing in a storage system is disclosed. In accordance with the present disclosure, a controller may take long term “lease” of a portion (e.g., an LBA range) of a virtual disk of a RAID system and then utilize local locks for IOs directed to the leased portion. The method and system in accordance with the present disclosure eliminates inter-controller communication for the majority of IOs and improves the overall performance for a High Availability…
CABLE EXIT METHODS FOR PCIE CARDS
Granted: March 27, 2014
Application Number:
20140087570
The present disclosure is directed to an apparatus configured for providing a plurality of exit routes to a single type of cable. The apparatus includes a board configured to have a notch. The notch is dimensioned to have a first predetermined distance from a lowest edge of the notch to a pin A1 location on the board and a second predetermined distance from an edge of the board to the pin A1 location. The apparatus also includes a plurality of connectors configured for receiving a cable…
Maximum Likelihood Bit-Stream Generation and Detection Using M-Algorithm and Infinite Impulse Response Filtering
Granted: March 27, 2014
Application Number:
20140086367
Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements…
PROCESSOR HAVING INSTRUCTION SET WITH USER-DEFINED NON-LINEAR FUNCTIONS FOR DIGITAL PRE-DISTORTION (DPD) AND OTHER NON-LINEAR APPLICATIONS
Granted: March 27, 2014
Application Number:
20140086361
A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software…
Software Digital Front End (SoftDFE) Signal Processing
Granted: March 27, 2014
Application Number:
20140086356
Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally…
DATA-DEPENDENT EQUALIZER CIRCUIT
Granted: March 27, 2014
Application Number:
20140086298
A data dependent equalizer circuit includes a plurality of noise prediction filters. Respective ones of the noise prediction filters are configured to filter noise in sample data for at least one predetermined non-return to zero (NRZ) condition. A plurality of equalizers is communicatively coupled with the plurality of noise prediction filters. Respective ones of the plurality of equalizers are configured to yield equalized sample data that corresponds to the at least one predetermined…
REAL TIME MRA ESTIMATION AND CORRECTION USING ADC SAMPLES
Granted: March 27, 2014
Application Number:
20140085743
Methods and systems for estimating MRA for a hard disk drive are described. The methods and systems described herein provide for real time estimating and correcting magneto-resistive head asymmetry (MRA) in a hard disk drive using analog-to-digital convertor (ADC) samples or counts. Generally, ADC outputs may be obtained by injecting MRA at known values, where an estimated MRA may be derived in real time by applying an equation using particular ADC output values. Once an estimated MRA is…
CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
Granted: March 27, 2014
Application Number:
20140084981
Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing…
SELF-JOURNALING AND HIERARCHICAL CONSISTENCY FOR NON-VOLATILE STORAGE
Granted: March 20, 2014
Application Number:
20140082261
A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams,…
