Uniform-Footprint Programmable-Skew Multi-Stage Delay Cell
Granted: March 20, 2014
Application Number:
20140082577
Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay…
Systems and Methods for Detector Side Trapping Set Mitigation
Granted: March 20, 2014
Application Number:
20140082461
Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.
MEASURING CELL DAMAGE FOR WEAR LEVELING IN A NON-VOLATILE MEMORY
Granted: March 20, 2014
Application Number:
20140082459
An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the…
Systems and Methods for Efficient Transfer in Iterative Processing
Granted: March 20, 2014
Application Number:
20140082450
Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for format efficient data processing.
SELF-JOURNALING AND HIERARCHICAL CONSISTENCY FOR NON-VOLATILE STORAGE
Granted: March 20, 2014
Application Number:
20140082261
A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams,…
MULTI-SERVER AGGREGATED FLASH STORAGE APPLIANCE
Granted: March 20, 2014
Application Number:
20140082258
A device for aggregating flash modules includes a switch to connect to a plurality of servers and a midplane to connect to a plurality of flash modules. The switch and midplane are connected such that the switch can route data traffic to any of the plurality of flash modules, and the plurality of servers can connect to the plurality of flash modules transparently, as if a flash module was directly installed into a server.
DIRECT DIGITAL SYNTHESIS OF QUADRATURE MODULATED SIGNALS
Granted: March 20, 2014
Application Number:
20140079154
An apparatus comprises a direct digital synthesizer, a mixer having first and second input ports and an output port, and a numerically-controlled oscillator. The direct digital synthesizer has a first output coupled to the first input port of the mixer and a second output coupled to a control input of the numerically-controlled oscillator, and the numerically-controlled oscillator has an output coupled to the second input port of the mixer. The mixer provides a quadrature modulated…
OPTIMIZED MECHANISM TO SIMPLIFY THE CIRCULANT SHIFTER AND THE P/Q KICK OUT FOR LAYERED LDPC DECODER
Granted: March 13, 2014
Application Number:
20140075261
A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.
READ-CHANNEL DESIGN AND SIMULATION TOOL HAVING A CODEWORD-CLASSIFICATION MODULE
Granted: March 13, 2014
Application Number:
20140075400
A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses codeword/waveform classification to accelerate simulation of the read-channel's error-rate characteristics, with said classification being generated using a first read-channel simulator having a limited functionality. A second read-channel simulator having an extended functionality is then run only for some of the codewords, with the…
CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING
Granted: March 13, 2014
Application Number:
20140075264
A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the…
STORAGE DEVICE CARRIERS FOR ADAPTING A STORAGE DEVICE OF A FIRST SIZE TO A SLOT FOR A STORAGE DEVICE OF A SECOND SIZE
Granted: March 13, 2014
Application Number:
20140070682
Apparatus and devices for carrying a storage device and adapting it to a slot for a storage device having a different form factor. The system comprises an opening means for elastically deforming a shape of the system from an original shape so that the carrier may receive the storage device. The system also comprises restraining means for constraining the motion of the storage device within the system when the system returns to the original shape. Furthermore, the system comprises a…
DIGITAL PROCESSOR HAVING INSTRUCTION SET WITH COMPLEX EXPONENTIAL NON-LINEAR FUNCTION
Granted: March 13, 2014
Application Number:
20140075162
A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential…
SCALABLE POWER MODEL CALIBRATION
Granted: March 13, 2014
Application Number:
20140074449
A high-frequency supply voltage waveform is sampled from a functioning integrated circuit. This waveform is measured at (or coupled closely to) a power supply node on the integrated circuit. A low-frequency supply current waveform is sampled concurrently with the sampling the high-frequency supply voltage waveform. This waveform is measured at a power supply node external to the integrated circuit. A power supply network providing power to the integrated circuit is modeled with a circuit…
BLOCK-BASED CREST FACTOR REDUCTION (CFR)
Granted: March 13, 2014
Application Number:
20140072073
Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data…
MEMORY DEVICE WITH CLOCK GENERATION BASED ON SEGMENTED ADDRESS CHANGE DETECTION
Granted: March 13, 2014
Application Number:
20140071783
A memory device comprises a memory array and associated control circuitry. The control circuitry comprises a clock generator configured to generate a clock signal for controlling timing of at least one of a read operation and a write operation directed to the memory array. The clock generator comprises a plurality of sets of address change detection circuits. The sets are configured to generate respective output signals as a function of respective subsets of address bits of an address…
ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY
Granted: March 13, 2014
Application Number:
20140071775
A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge…
STORAGE DEVICE HAVING DEGAUSS CIRCUITRY GENERATING DEGAUSS SIGNAL WITH MULTIPLE DECAY SEGMENTS
Granted: March 13, 2014
Application Number:
20140071561
A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a degauss signal to be applied to the write head by the write driver. The degauss signal has a waveform comprising a plurality of decay segments including at…
POWER MANAGEMENT FOR STORAGE DEVICE READ CHANNEL
Granted: March 13, 2014
Application Number:
20140071558
A hard disk drive or other storage device comprises a storage medium, a read head configured to read data from the storage medium, and control circuitry coupled to the read head and configured to process data received from the read head. The control circuitry comprises read channel circuitry that includes a low-density parity check decoder or other type of decoder. Power management circuitry associated with the read channel circuitry is configured to detect a power control condition of…
TRACK-AND-HOLD CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER WITH SWITCHED CAPACITOR COUPLING OF AMPLIFIER STAGE
Granted: March 13, 2014
Application Number:
20140070971
A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second…
METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS
Granted: March 13, 2014
Application Number:
20140070849
Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock…
