Direct Digital Synthesis Of Signals Using Maximum Likelihood Bit-Stream Encoding
Granted: March 6, 2014
Application Number:
20140064417
Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype…
INTEGRATED CIRCUIT CHARACTERIZATION BASED ON MEASURED AND STATIC APPARENT RESISTANCES
Granted: March 6, 2014
Application Number:
20140068532
First and second apparent resistance measures are determined for an integrated circuit and utilized to characterize the integrated circuit. The first apparent resistance measure is determined for the integrated circuit based on a first voltage drop and a first current that are measured using test equipment. The second apparent resistance measure is determined for the integrated circuit based on a second voltage drop and a second current that are obtained using static analysis of a…
OPTIMIZED SCHEME AND ARCHITECTURE OF HARD DRIVE QUEUE DESIGN
Granted: March 6, 2014
Application Number:
20140068389
Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least…
INSTRUCTION ADDRESS ENCODING AND DECODING BASED ON PROGRAM CONSTRUCT GROUPS
Granted: March 6, 2014
Application Number:
20140068229
Coding circuitry comprises at least an encoder configured to encode an instruction address for transmission to a decoder. The encoder is operative to identify the instruction address as belonging to a particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to encode the instruction address based on the identified group. The decoder is operative to identify the encoded instruction address as belonging to the particular…
ELASTIC CACHE WITH SINGLE PARITY
Granted: March 6, 2014
Application Number:
20140068181
The invention provides an elastic or flexible SSD cache utilizing a hybrid RAID protocol combining RAID-0 protocol for read data and RAID-5 single parity protocol for write data in the same cache array. Read data may be stored in window sized allocations using RAID-0 protocol to avoid allocating an entire RAID stripe for read cache data. In the same SSD volume, dirty write data is stored in row allocations using RAID-5 protocol to provide single parity for the dirty write data. Read data…
ENHANCED MEMORY SAVINGS IN ROUTING MEMORY STRUCTURES OF SERIAL ATTACHED SCSI EXPANDERS
Granted: March 6, 2014
Application Number:
20140068177
Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The…
EFFICIENT MEMORY CONTENT ACCESS
Granted: March 6, 2014
Application Number:
20140068164
A memory content access interface may include, but is not limited to: a read-path memory partition; a write-path memory partition; and a memory access controller configured to regulate access to at least one of the read-path memory partition and the write-path memory partition by an external controller.
MEMORY THROUGHPUT IMPROVEMENT USING ADDRESS INTERLEAVING
Granted: March 6, 2014
Application Number:
20140068125
Aspects of the disclosure pertain to a system and method for promoting memory throughput improvement in a multi-processor system. The system and method implement address interleaving for promoting memory throughput improvement. The system and method cause memory access requests to be selectively routed from master devices to slave devices based upon a determined value of a selected bit of an address specified in the memory access request.
ENHANCED MEMORY SAVINGS IN ROUTING MEMORY STRUCTURES OF SERIAL ATTACHED SCSI EXPANDERS
Granted: March 6, 2014
Application Number:
20140068124
Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The…
PROCESS TO GENERATE VARIOUS LENGTH PARAMETERS IN A NUMBER OF SGLS BASED UPON THE LENGTH FIELDS OF ANOTHER SGL
Granted: March 6, 2014
Application Number:
20140067877
A method of generating length parameters, comprising the steps of reading a data stream from a host, detecting a particular field of the data stream, and calculating a variable based on a length parameter of a first list to be transferred. The data stream may comprise a plurality of definitions. The method may also comprise the step of selecting one of the list definitions. One of the list definitions may be used to generate a length parameter used in a second list in response to (i) the…
CROSSING ISI CANCELLATION
Granted: March 6, 2014
Application Number:
20140064353
An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.
PREAMBLE DETECTION USING VECTOR PROCESSORS
Granted: March 6, 2014
Application Number:
20140064338
In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a…
Scalable Storage Protection
Granted: March 6, 2014
Application Number:
20140064048
The disclosure is directed to protecting data of a scalable storage system. A scalable storage system includes a plurality of nodes, each of the nodes having directly-attached storage (DAS), such as one or more hard-disk drives and/or solid-state disk drives. The nodes are coupled via an inter-node communication network, and a substantial entirety of the DAS is globally accessible by each of the nodes. The DAS is protected utilizing intra-node protection to keep data stored in the DAS…
READ SELF-TIME TECHNIQUE WITH FINE GRAINED PROGRAMMABLE LOGIC DELAY ELEMENT
Granted: March 6, 2014
Application Number:
20140063917
A sense amplifier enable signal delay circuit for the programmable control of the delay of the generation of a sense amplifier enable signal is described. Further, stacked transistors and a pulse-width control block, which are programmed by external test pins to control the delay of the generation of a sense amplifier enable signal are described. Methods associated with the use of the sense amplifier enable signal delay circuit and for the sense amplifier enable signal generation delay…
REAL TIME CLOSE LOOP FLY HEIGHT CONTROL
Granted: February 27, 2014
Application Number:
20140055882
A device includes a disk drive assembly configured to store information using a platter comprising a magnetic material surface and a magnetic head disposed above the magnetic material surface. The magnetic head is configured to move across tracks formed on the platter to write information to the magnetic material surface and read information from the magnetic material surface. The device also includes a controller operatively coupled with the disk drive assembly. The controller is…
DYNAMIC Y-BUFFER SIZE ADJUSTMENT FOR RETAINED SECTOR REPROCESSING
Granted: February 27, 2014
Application Number:
20140059377
Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system.
STORAGE DEVICE FIRMWARE AND MANUFACTURING SOFTWARE
Granted: February 27, 2014
Application Number:
20140059278
Storage device FirmWare (FW) and manufacturing software techniques include access to FW images and communication of a manufacturing software tool. The manufacturing software tool enables download of the FW images into an I/O device and controlling a manufacturing test of the I/O device that is a storage device providing a storage capability. Execution of the downloaded FW images enables an I/O controller of the I/O device to provide the storage capability via operation with one or more…
NON-DISRUPTIVE SELECTIVE TRAFFIC BLOCKING IN A SAS DOMAIN
Granted: February 27, 2014
Application Number:
20140059256
The invention may be embodied in a SAS expander with register bits within Phys associated with I/O devices. Setting and unsetting the register bit in the Phy associated with a particular physical or logical device allows I/O traffic to be blocked and unblocked, as desired, to the selected physical or logical devices. In a particular embodiment, when the register bit is set to a blocking state, an OPEN request that comes in on the SAS link is rejected using OPEN_REJECT (RETRY). Phy…
METHODS AND STRUCTURE FOR IDENTIFYING SUPPORT FOR SUPER-STANDARD FEATURES IN COMMUNICATIONS BETWEEN SERIAL ATTACHED SCSI DEVICES
Granted: February 27, 2014
Application Number:
20140059253
Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents…
ENHANCED MOBILE DEVICE HAVING MULTIPLE HOUSING CONFIGURATIONS
Granted: February 27, 2014
Application Number:
20140057682
An apparatus comprises a first housing having a top surface and a bottom surface, a second housing having a top surface and a bottom surface, and one or more supports coupling the first housing to the second housing such that the first and second housings are electrically connected and the bottom surface of the first housing overlays the top surface of the second housing. The one or more supports are configurable in at least a first configuration wherein the bottom surface of the first…
