METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CORRECT-BY-CONSTRUCTION PROGRESSIVE MODELING AND AN APPARATUS EMPLOYING THE METHOD
Granted: February 27, 2014
Application Number:
20140059505
Methods of designing an integrated circuit and an apparatus for designing an integrated circuit are disclosed herein. In one embodiment, a method includes: (1) generating a block model of the integrated circuit according to a first timing budget, (2) developing a top level implementation of the integrated circuit according to the first timing budget, (3) determining a second timing budget for the integrated circuit based on the block model and (4) modifying the block model and the top…
ACCELERATOR FOR A READ-CHANNEL DESIGN AND SIMULATION TOOL
Granted: February 20, 2014
Application Number:
20140053121
A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously…
Method for Selecting a LDPC Candidate Code
Granted: February 20, 2014
Application Number:
20140053038
A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.
METHODS AND STRUCTURE FOR NORMALIZING STORAGE PERFORMANCE ACROSS A PLURALITY OF LOGICAL VOLUMES
Granted: February 20, 2014
Application Number:
20140052908
Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance…
FILE DELETION FOR NON-VOLATILE MEMORY
Granted: February 20, 2014
Application Number:
20140052893
A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file. The controller stores the data at a data storage segment having a physical address and associates the physical address with the logical address and a file identifier for the file. The controller receives a second write request including data and the logical address associated with the file. The controller stores the data at a second…
METHODS AND STRUCTURE FOR ANALYZING DIFFERENT SIGNALING PATHWAYS THROUGH A TEST SIGNAL SELECTION HIERARCHY
Granted: February 20, 2014
Application Number:
20140052404
Methods and structure are disclosed for analyzing different signaling pathways through a test signal selection hierarchy utilizing test patterns. One embodiment comprises an integrated circuit that includes a block of circuitry, a test signal generator, and a test signal selection hierarchy. The block of circuitry generates internal operational (TOP) signals for performing functions. The test signal generator generates test patterns that correspond with the IOP signals. The test signal…
MEMORY DEVICE HAVING COLLABORATIVE FILTERING TO REDUCE NOISE
Granted: February 20, 2014
Application Number:
20140050023
An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured…
LOCALIZED DEVICE MISSING DELAY TIMERS IN SAS/SATA TOPOLOGY
Granted: February 13, 2014
Application Number:
20140047136
A SAS expander includes DMD timers for each PHY so that the expander can track disconnected devices directly connected to the expander and signal a SAS controller when the DMD is exceeded. A system including such SAS expanders may reduce the load on the system controller. A controller may recognize expanders capable of tracking DMDs for backwards compatibility.
TRIM MECHANISM USING MULTI-LEVEL MAPPING IN A SOLID-STATE MEDIA
Granted: February 13, 2014
Application Number:
20140047210
Described embodiments provide a media controller that receives requests that include a logical address and address range. In response to the request, the media controller determines whether the received request is an invalidating request. If the received request type is an invalidating request, the media controller uses a map to determine one or more entries of the map associated with the logical address and range. Indicators in the map associated with each of the map entries are set to…
MAINTAINING ORDERING VIA A MULTI-LEVEL MAP OF A SOLID-STATE MEDIA
Granted: February 13, 2014
Application Number:
20140047170
Described embodiments provide a media controller that processes requests including a logical address and address range. A map of the media controller determines physical addresses of a media associated with the logical address and address range of the request. The map is a multi-level map having a plurality of leaf-level map pages that are stored in the media, with a subset of the leaf-level map pages stored in a map cache. Based on the logical address and address range, it is determined…
METHODS AND STRUCTURE FOR HARDWARE MANAGEMENT OF SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA) DMA NON-ZERO OFFSETS IN A SERIAL ATTACHED SCSI (SAS) EXPANDER
Granted: February 13, 2014
Application Number:
20140047134
Methods and structure for enhanced SAS expander functionality to store and forward buffered information transmitted from a SATA end device to an STP initiator device while managing use of Non-Zero Offset (“NZO”) field values in DMA Setup FISs transmitted by the SATA end device. The enhanced expander establishes a connection between an STP initiator and a SATA end device. The expander forwards a read command from the initiator to the end device. If NZO use is supported and enabled in…
MULTI-CHIP STACKING OF INTEGRATED CIRCUIT DEVICES USING PARTIAL DEVICE OVERLAP
Granted: February 13, 2014
Application Number:
20140042601
One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A…
OPTIMIZED MULTI-LEVEL FINITE STATE MACHINE WITH REDUNDANT DC NODES
Granted: February 6, 2014
Application Number:
20140035692
A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality…
SINGLE-READ BASED SOFT-DECISION DECODING OF NON-VOLATILE MEMORY
Granted: February 6, 2014
Application Number:
20140040531
A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates…
MIXED GRANULARITY HIGHER-LEVEL REDUNDANCY FOR NON-VOLATILE MEMORY
Granted: February 6, 2014
Application Number:
20140040530
Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in…
SYSTEMS AND METHODS FOR TAG INFORMATION VALIDATION IN WIDE PORT SAS CONNECTIONS
Granted: February 6, 2014
Application Number:
20140040465
Methods and structures for validating tag information received in SAS frames by any of a plurality of ports comprising a SAS wide port. Each port may have a dedicated transport layer processing element. A tag information table is shared by all of the one or more transport layer processing elements. The tag information table is used to store information regarding a particular tag value being valid for use with a particular device and is updated when the particular tag value is no longer…
HIGH SPEED ADD-COMPARE-SELECT CIRCUIT
Granted: February 6, 2014
Application Number:
20140040342
In described embodiments, a trellis decoder includes a memory including a set of registers; and an add-compare-select (ACS) module including at least two ACS layer modules coupled in series and configured to form a feedback loop with carry components in a single clock cycle, wherein the ACS layer module includes at least two branch metrics represented by a plurality of bits and adders configured to generate a plurality of state metrics using carry-save arithmetic, and a plurality of…
METHODS AND STRUCTURE FOR REDUCED LAYOUT CONGESTION IN A SERIAL ATTACHED SCSI EXPANDER
Granted: February 6, 2014
Application Number:
20140036699
Methods and structure for reduced layout congestion in a switching device integrated circuit. A switching device such as a Serial Attached SCSI (SAS) expander comprises a switching circuit to couple any of a plurality (“N”) of physical links of the switching device with any other physical link of the switching device. The switching circuit comprises a first stage circuit adapted to couple any of the N physical links with a selected one of N/2 communication paths of the switching…
BTI-Independent Source Biasing of Memory Arrays
Granted: February 6, 2014
Application Number:
20140036612
A memory device having an array of memory cells and BTI-independent bias circuitry for controlling the bias voltage level of a source node of the array. The bias circuitry has an n-type transistor and a p-type transistor connected in parallel between ground and the source node. The bias circuitry also has circuitry for controlling the n-type and p-type transistors such that the memory device can be selectively configured in any of an active mode (where the source node is driven towards…
ZERO GAIN START BIAS ESTIMATION
Granted: February 6, 2014
Application Number:
20140036385
A method and system for estimating a zero gain start (ZGS) bias in a read channel is disclosed. The method may include: receiving preamble samples within a fixed-length window selected for ZGS calculation; calculating an energy associated with a 2T frequency in the preamble samples; calculating an energy associated with non-2T frequencies in the preamble samples; and calculating the ZGS bias based on the energy associated with the 2T frequency in the preamble samples and the energy…
