SYSTEM AND METHOD FOR GENERATING PHYSICAL DETERMINISTIC BOUNDARY INTERCONNECT FEATURES FOR DUAL PATTERNING TECHNOLOGIES
Granted: February 6, 2014
Application Number:
20140040847
One aspect provides a system for generating a layout for dual patterning technologies. In one embodiment, the system includes: (1) a deterministic boundary interconnect feature generator configured to generate a deterministic boundary interconnect feature for a cell based on at least one dual patterning design rule; and (2) cell placement and interconnect routing tools associated with the deterministic boundary interconnect feature generator and configured to place the deterministic…
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
Granted: February 6, 2014
Application Number:
20140040842
A method of reducing total power dissipation for logic cells using Boolean equations includes selecting a path, identifying at least one group of logic cells for analysis in the path, and deriving Boolean equations for the at least one group of logic cells. Additionally, the method includes listing possible logic cell implementations for each Boolean equation while maintaining original transistor values, verifying path timing for the possible logic cell implementations to provide…
SOFT-DECISION COMPENSATION FOR FLASH CHANNEL VARIATION
Granted: February 6, 2014
Application Number:
20140040704
In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a…
METHOD AND SYSTEM FOR SYMBOL ERROR RATE ESTIMATION AND SECTOR QUALITY MEASUREMENT
Granted: February 6, 2014
Application Number:
20140040682
A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also…
METHODS AND STRUCTURE FOR TRAPPING REQUESTS DIRECTED TO HARDWARE REGISTERS OF AN ELECTRONIC CIRCUIT
Granted: February 6, 2014
Application Number:
20140040672
Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further…
ENCRYPTED-TRANSPORT SOLID-STATE DISK CONTROLLER
Granted: February 6, 2014
Application Number:
20140040639
An encrypted transport SSD controller has an interface for receiving commands, storage addresses, and exchanging data with a host for storage of the data in a compressed (and optionally encrypted) form in Non-Volatile Memory (NVM), such as flash memory. Encrypted data received from the host is decrypted and compressed using lossless compression for advantageously reducing flash memory write amplification. The compressed data is re-encrypted and stored in the flash memory. The stored data…
SYSTEMS AND METHODS FOR INFORMATION SECURITY USING ONE-TIME PAD
Granted: January 30, 2014
Application Number:
20140032937
Methods of encryption and decryption using a key generated from a common document are disclosed. In one embodiment, the method of encryption includes: (1) generating a single pointer to a position in a common document, wherein the pointer includes either a page number and a line number of the common document or a chapter number and a paragraph number of the common document, (2) receiving a message to be encrypted, (3) retrieving, from a computer memory, a key from the common document…
FLAW SCAN CIRCUIT FOR REPEATABLE RUN OUT (RRO) DATA
Granted: January 30, 2014
Application Number:
20140033000
Improved flaw scan circuits are provided for repeatable run out data. RRO (repeatable run out) data is processed by counting a number of RRO data bits detected in a servo sector; and setting an RRO flaw flag if at least a specified number of RRO data bits is not detected in the server sector. The RRO flaw flag can also optionally be set by detecting an RRO address mark in the servo sector; counting a number of samples in the servo sector after the RRO address mark that do not satisfy a…
SCAN TEST CIRCUITRY CONFIGURED TO PREVENT CAPTURE OF POTENTIALLY NON-DETERMINISTIC VALUES
Granted: January 30, 2014
Application Number:
20140032985
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent the scan cell from capturing a potentially non-deterministic value from a portion of the additional circuitry. The portion of the additional circuitry that provides the…
METHODS AND STRUCTURE FOR HARDWARE SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA) ERROR RECOVERY IN A SERIAL ATTACHED SCSI (SAS) EXPANDER
Granted: January 30, 2014
Application Number:
20140032979
Methods and structure for enhanced SAS expander functionality to store and forward buffered information transmitted from an initiator device to a target device and to process errors in control circuits of the expander without intervention from the general purpose programmable processor of the expander. A PHY of an expander is associated with control circuits that comprise buffering of commands to be forwarded to an end device directly coupled to the PHY. The control circuits locally…
CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTIVE VOLTAGE SCALING AND METHOD OF OPERATION THEREOF
Granted: January 30, 2014
Application Number:
20140028364
A critical path monitor (CPM), a method of setting supply voltage based on output of a CPM and an integrated circuit (IC) incorporating the CPM. In one embodiment, the CPM includes: (1) an edge detector configured to produce a thermometer output over a plurality of clock cycles and (2) a min_max recorder, coupled to the edge detector and configured to record minimum and maximum values of the thermometer output during a polling interval.
HYBRID STORAGE DEVICE HAVING DISK CONTROLLER WITH HIGH-SPEED SERIAL PORT TO NON-VOLATILE MEMORY BRIDGE
Granted: January 30, 2014
Application Number:
20140032814
A hybrid storage device comprises at least one storage disk, a disk controller configured to control writing of data to and reading of data from the storage disk, a non-volatile electronic memory, and a bridge device coupled between the disk controller and the non-volatile electronic memory. The disk controller comprises a plurality of high-speed serial interfaces. In one embodiment, the high-speed serial interfaces include a first high-speed serial interface configured to interface the…
Parameterized Digital Divider
Granted: January 30, 2014
Application Number:
20140032622
A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The…
ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES DURING CU/LOW-K BEOL PROCESSING
Granted: January 30, 2014
Application Number:
20140030541
Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can he provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper…
MEMORY DEVICE WITH SEPARATELY CONTROLLED SENSE AMPLIFIERS
Granted: January 30, 2014
Application Number:
20140029366
A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control…
BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM
Granted: January 30, 2014
Application Number:
20140029364
DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification…
STORAGE DEVICE HAVING DEGAUSS CIRCUITRY WITH RAMP GENERATOR FOR USE IN GENERATING CHIRPED DEGAUSS SIGNAL
Granted: January 30, 2014
Application Number:
20140029138
A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a chirped degauss signal to be applied to the write head by the write driver. The degauss circuitry comprises a ramp generator configured to generate a ramp…
METHODS AND APPARATUS FOR IMPROVED DETECTION OF SERVO SECTOR DATA USING SINGLE BIT ERROR CORRECTION
Granted: January 30, 2014
Application Number:
20140029129
Methods and apparatus are provided for improved detection of servo sector data in a magnetic recording system using single bit error correction. Servo sector data is processed by detecting the servo sector data; determining whether a single bit error occurred in the detected servo sector data; and flipping a bit value of an individual bit in the detected servo sector data having a lowest amplitude sample among the samples of the detected servo sector data when a single bit error is…
Over-the-Rail Write Driver for Magnetic Storage Systems
Granted: January 30, 2014
Application Number:
20140029127
A write driver circuit for generating a write current pulse for use by a magnetic write head includes an output stage adapted for connection with the magnetic write head and a charge storage circuit connected with the output stage. The charge storage circuit is operative in a first mode to store a prescribed charge and is operative in a second mode to transfer at least a portion of the charge stored therein to the output stage to thereby enable an output voltage level of the output stage…
Low-Voltage Active Inductor
Granted: January 30, 2014
Application Number:
20140028416
An active inductor circuit includes a field-effect transistor having a first source/drain adapted for connection with a first voltage source, a capacitor coupled between the first voltage source and a gate of the field-effect transistor, a resistor coupled between a second source/drain of the field-effect transistor and the gate of the field-effect transistor, and a current source coupled with the gate of the field-effect transistor. A voltage headroom of the active inductor circuit is…
