ACCELERATING ERROR-CORRECTION DECODER SIMULATIONS WITH THE ADDITION OF ARBITRARY NOISE
Granted: January 16, 2014
Application Number:
20140019825
In one embodiment, a simulator, e.g., for a hard-disk drive selects for testing a signal-to-noise ratio (SNR) value from a range of ratios and an error-correction codeword pattern from a range of codeword patterns. The simulator simulates a communications channel by applying write noise, inter-symbol interference, and read noise to the codeword pattern to generate a noisy signal. In addition, the simulator adds arbitrary-noise to the codeword to accelerate the speed of the simulation.…
HIGH DENSITY DISK DRIVE PERFORMANCE ENHANCEMENT SYSTEM
Granted: January 16, 2014
Application Number:
20140019681
The present invention provides an HDD performance enhancement system that utilizes excess disk capacity as cache memory to enhance the I/O performance of the drive. The cache memory is distributed throughout the disk, for example in alternating tracks, sectors dedicated to serving as cache, or other distributed cache track segments or segment groups. Distributing the cache throughout the disk reduces the physical distance of the I/O head to the closest available cache location. The…
METHODS AND STRUCTURE ENHANCING ZONE CONFIGURATION IN A SERIAL ATTACHED SCSI ENVIRONMENT
Granted: January 16, 2014
Application Number:
20140019645
Methods and structure are provided for enhancing zone configuration processes in a Serial Attached SCSI (SAS) architecture. The method includes embedding, at a SAS initiator, a ZONE UNLOCK request within a Serial Management Protocol (SMP) ZONE ACTIVATE command. The method also comprises transmitting the SMP ZONE ACTIVATE command to a SAS expander, and receiving, at the SAS expander, the SMP ZONE ACTIVATE command. Further, the method includes detecting, at the SAS expander, the ZONE…
SYSTEM FOR INJECTING PROTOCOL SPECIFIC ERRORS DURING THE CERTIFICATION OF COMPONENTS IN A STORAGE AREA NETWORK
Granted: January 9, 2014
Application Number:
20140013152
An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.
Systems and Methods for Filter Initialization and Tuning
Granted: January 9, 2014
Application Number:
20140012888
Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to…
High-Speed Sensing Scheme for Memory
Granted: January 2, 2014
Application Number:
20140003160
A sensing circuit for use in a memory including memory cells and at least one bitline coupled with the memory cells includes first and second sense amplifiers and a controller coupled with the sense amplifiers. The first sense amplifier is adapted to read a selected one of the memory cells coupled to the first sense amplifier via a corresponding bitline. The second sense amplifier is adapted to read a selected one of the memory cells coupled to the second sense amplifier via a…
Source Code Generator for Software Development and Testing for Multi-Processor Environments
Granted: January 2, 2014
Application Number:
20140007044
In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors. The system comprising a plurality of processors of two or more different processor types. Machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building…
Program Module Applicability Analyzer for Software Development and Testing for Multi-Processor Environments
Granted: January 2, 2014
Application Number:
20140007043
In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT…
Source Code Level Multistage Scheduling Approach for Software Development and Testing for Multi-Processor Environments
Granted: January 2, 2014
Application Number:
20140006751
In one embodiment, a heterogeneous multi-processor computer system includes (i) a plurality of dedicated processors (DPs), each DP configured to implement one or more program modules during runtime operations; (ii) two or more control processors (CPs), each CP configured to run scheduling software for controlling the runtime operations by a corresponding subset of DPs; and (iii) one or more buses interconnecting the DPs and CPs. Each CP is configured to vary timing of implementation of…
Address Remapping Using Interconnect Routing Identification Bits
Granted: January 2, 2014
Application Number:
20140006644
A method for mapping addresses between one or more master devices and at least one common slave device in a multiprocessor system is provided, the system including a bus interconnect for interfacing between the master devices and the common slave device. The method includes steps of: receiving a first address corresponding to a bus transaction between a given one of the one or more master devices and the common slave device; decoding a unique identifier associated with the given one of…
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
Granted: December 26, 2013
Application Number:
20130346932
A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis…
DYNAMICALLY CONTROLLING THE NUMBER OF LOCAL ITERATIONS IN AN ITERATIVE DECODER
Granted: December 26, 2013
Application Number:
20130346824
An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is…
APPARATUS AND METHOD FOR BREAKING TRAPPING SETS
Granted: December 26, 2013
Application Number:
20130343495
An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a…
ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY
Granted: December 26, 2013
Application Number:
20130343139
A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays…
FAST TRACKING FOR FLASH CHANNELS
Granted: December 26, 2013
Application Number:
20130343131
An SSD controller dynamically adjusts read thresholds in an NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller periodically performs offline tracking on a portion of the NVM. The controller reads a representative sub-portion with current read thresholds. If the read meets a condition, then the controller reads the sub-portion with sample…
OPTICAL SOURCE DRIVER CIRCUIT HAVING OVERSHOOT CONTROLLER
Granted: December 19, 2013
Application Number:
20130336663
A driver circuit configured to generate a drive signal for an optical source comprises an overshoot controller that provides an amount of overshoot for a given logic state of the drive signal as a function of a duration of at least one previous logic state of the drive signal. The drive signal may alternate between a first logic state associated with a first operating mode of the optical source and a second logic state associated with a second operating mode of the optical source. The…
SMART ACTIVE-ACTIVE HIGH AVAILABILITY DAS SYSTEMS
Granted: December 19, 2013
Application Number:
20130339786
A high availability DAS system uses a solid state cache to provide near active-active performance in a DAS duster, while retaining the implementation simplicity of active-passive or dual active system. Each node in the duster may include a solid state cache that stores hot I/O in an active-active mode, which allows the data to be read from or written to the underlying dual-active or active/passive DAS RAID system only when access to the “hot Region” cools down or in the case of Cache…
METHODS AND SYSTEMS FOR ADAPTIVE QUEUE DEPTH MANAGEMENT
Granted: December 19, 2013
Application Number:
20130339599
The invention may be embodied in a multiple-disk data storage system including a controller module that initiates an optimization algorithm to set maximum queue depth of each disk of the data storage system to desired queue depth of each disk. Desired queue depth of each disk may be associated with performance factors including, but not limited to, input/output operations per second (IOPs), average response time, and/or maximum response time of each disk. Desired queue depth of each disk…
HOST BUS ADAPTERS WITH SHARED MEMORY AND BATTERY BACKUP
Granted: December 19, 2013
Application Number:
20130339594
The present disclosure includes methods and systems that share memory located on one PCIe based HBA across other PCIe based HBAs in the system. In addition, the backup battery is effectively shared across multiple PCIe based HBAs in the system. This approach saves significant costs by avoiding the need to have a separate DRAM with its own dedicated battery backup on each HBA board in the system. This also allows the redundant memory and backup batteries to be removed while still…
SYSTEMS AND METHODS FOR ADVANCED INTERRUPT SCHEDULING AND PRIORITY PROCESSING IN A STORAGE SYSTEM ENVIRONMENT
Granted: December 19, 2013
Application Number:
20130339563
Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt…
