Acceleration of Software Modifications in Networked Devices
Granted: December 19, 2013
Application Number:
20130339940
A method of modifying software associated with network devices includes transmitting a modification message by a first network device in response to software associated with the first network device being modified; transmitting second software identification information by a second network device in response to receiving the modification message from the first network device; providing a database comprising the first product identifier, the second product identifier, first software…
HIERARCHICAL DESIGN FLOW GENERATOR
Granted: December 19, 2013
Application Number:
20130339912
A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow…
POWER-GATED MEMORY DEVICE WITH POWER STATE INDICATION
Granted: December 12, 2013
Application Number:
20130332763
A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
Techniques For Reducing A Rate Of Data Transfer To At Least A Portion Of Memory
Granted: December 12, 2013
Application Number:
20130332689
A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation.
METHODS AND APPARTUS FOR PERFORMING POWER ESTIMATION IN CIRCUITS
Granted: December 12, 2013
Application Number:
20130332142
Power consumption is estimated for an application being executed by a circuit. Power consumption values are estimated for a set of base events executed by the circuit. The application is then reduced to an equivalent sequence of base events selected from the set of base events. Lastly, the estimated power consumption values for the base events in the equivalent sequence of base events are summed.
Memory Device Having Control Circuitry for Write Tracking Using Feedback-Based Controller
Granted: December 5, 2013
Application Number:
20130322190
A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory…
METHODS AND STRUCTURE FOR IMPLEMENTING SECURITY IN SYSTEMS THAT UTILIZE SMALL COMPUTER SYSTEM INTERFACE ENCLOSURE SERVICES
Granted: December 5, 2013
Application Number:
20130326615
Methods and structure are provided for implementing security features in SCSI Enclosure Services (SES) systems. The system comprises an SES device server, which includes a frontend interface, control unit, and backend interface. The frontend interface is operable to receive SES commands generated by Small Computer System Interface (SCSI) devices, and the backend interface is operable to manage operations of at least one peripheral device communicatively coupled with the SES device server…
Techniques for increasing a lifetime of blocks of memory
Granted: December 5, 2013
Application Number:
20130326130
Techniques are described for increasing a lifetime of a plurality of blocks of memory by equalizing a variation between the blocks. In operation, blocks to be written are allocated from a set of blocks having a lifetime factor below a threshold. The threshold is reset as required to resupply the set of blocks available for allocation.
METHODS AND STRUCTURE FOR ACCOUNTING FOR CONNECTION RESETS BETWEEN PERIPHERAL COMPONENT INTERCONNECT EXPRESS BRIDGES AND HOST DEVICES
Granted: December 5, 2013
Application Number:
20130326106
Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag…
Conditional Read-Assist Feature to Accelerate Access Time in an Electronic Device
Granted: December 5, 2013
Application Number:
20130322194
An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second…
UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL
Granted: December 5, 2013
Application Number:
20130321054
Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay…
PULSE SYNCHRONIZER CIRCUIT
Granted: December 5, 2013
Application Number:
20130321043
A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination…
Analog-to-Digital Converter With Power Supply-Based Reference
Granted: November 28, 2013
Application Number:
20130314110
A measurement circuit is provided for measuring the resistance of a variable resistance element biased with an external voltage supply. The measurement circuit includes an analog-to-digital converter (ADC) and a reference generator connected with the ADC. The ADC is operative to receive a reference voltage and a first voltage developed across the variable resistance element, and to generate a digital output signal indicative of a relationship between the first voltage and the reference…
Memory Management Scheme and Apparatus
Granted: November 28, 2013
Application Number:
20130318322
A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the…
SELECTIVE ENABLEMENT OF OPERATING MODES OR FEATURES VIA HOST TRANSFER RATE DETECTION
Granted: November 28, 2013
Application Number:
20130318289
Selective enablement of operating modes or features of a storage system via host transfer rate detection enables, in some situations, enhanced performance. For example, a Solid-State Disk (SSD) having a serial interface compatible with a particular serial interface standard selectively enables coalescing of status information for return to a host based on detecting a particular host transfer rate capability. Some hosts are not fully compliant with the particular standard, being unable to…
Electronic Storage System Architecture
Granted: November 28, 2013
Application Number:
20130314819
An electronic storage system includes a first cylindrical storage area. The first cylindrical storage area is configured to rotate about an axis. The first cylindrical storage area includes a first storage surface. The storage system further includes a first access head, configured to access information stored on the first storage surface, and a first head arm. The first access head is disposed on the first head arm. A corresponding method, cylindrical storage area, and head access…
Voice Band Data Mode in a Universal Facsimile Engine
Granted: November 28, 2013
Application Number:
20130314741
A facsimile apparatus includes a user interface operative to facilitate communications between the apparatus and at least one user application in operative communication with the apparatus, a network interface operative to facilitate communications between the apparatus and an analog communications network and an IP communications network. The apparatus further includes a controller connected to the user interface and network interface. The controller is operative in a first mode to…
OPTICAL SOURCE DRIVER CIRCUIT WITH CONTROLLABLE TERMINATION
Granted: November 21, 2013
Application Number:
20130308431
A driver circuit for a laser diode or other optical source comprises a controllable termination for a transmission line coupled between the driver circuit and the optical source, with the controllable termination being switchable between at least first and second termination configurations. The transmission line comprises a first conductor coupled to a first terminal of the optical source and a second conductor coupled to a second terminal of the optical source, and the driver circuit…
MEMORY DEVICE HAVING CONTROL CIRCUITRY CONFIGURED FOR CLOCK-BASED WRITE SELF-TIME TRACKING
Granted: November 21, 2013
Application Number:
20130308398
A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel…
Self-Calibrating Differential Current Circuit
Granted: November 21, 2013
Application Number:
20130307518
In one embodiment, a constant-current generator is connected in series with a dependent (e.g., tail) device. A switched capacitor circuit connected to the gate of the dependent device is operated to (i) charge at least one capacitor of the switched capacitor circuit, (ii) use the at least one charged capacitor to adjust the gate voltage of the dependent device to drive the dependent current through the dependent device to be equal to the constant current through the constant-current…
