SCAN CONTROLLER CONFIGURED TO CONTROL SIGNAL VALUES APPLIED TO SIGNAL LINES OF CIRCUIT CORE INPUT INTERFACE
Granted: November 21, 2013
Application Number:
20130311843
An integrated circuit comprises a memory or other circuit core having an input interface and an output interface, scan circuitry comprising at least one scan chain having a plurality of scan cells, and additional circuitry associated with at least one of the input interface and the output interface and testable utilizing said at least one scan chain. The scan circuitry further comprises a scan controller configured to control signal values applied to one or more signal lines of the input…
STORAGE PROCESSOR FOR EFFICIENT SCALING OF SOLID STATE STORAGE
Granted: November 21, 2013
Application Number:
20130311696
An SSD controller with two SAS interfaces includes an internal switch or expander to allow the SSD controller to function as both an initiator and target. Data packets received through one of the SAS interfaces may be directed to solid state memory elements directly connected to the SSD controller, or to one or more devices connected to the other SAS interface.
MULTI-PASS ROUTING TO REDUCE CROSSTALK
Granted: November 14, 2013
Application Number:
20130305203
An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.
METHODS AND STRUCTURE FOR CONFIGURING A SERIAL ATTACHED SCSI DOMAIN VIA A UNIVERSAL SERIAL BUS INTERFACE OF A SERIAL ATTACHED SCSI EXPANDER
Granted: November 14, 2013
Application Number:
20130304952
Methods and structure are provided for managing a Serial Attached SCSI (SAS) domain via Universal Serial Bus (USB) communications. The system comprises a SAS expander. The SAS expander comprises a plurality of physical links, a USB interface, and a control unit. The control unit is operable to receive USB packets via the USB interface, to determine SAS management information based upon the received USB packets, and to alter a configuration of the SAS domain based upon the SAS management…
METHODS AND STRUCTURE FOR IMPROVED AND DYNAMIC ZONING IN SERIAL ATTACHED SCSI EXPANDERS
Granted: November 14, 2013
Application Number:
20130304951
Methods and structure for dynamically modifying SAS Zoning Features of a SAS expander based on present operating status of the expander. Rules are provided and interpreted within the expander to define changes to be made to the present SAS Zoning Features based on changes to the present operating status of the expander. The present operating status may be, for example, the present day, date, time of day, etc. Exemplary rules may define a modification to the zone group identifier to be…
METHOD FOR BROADCAST PROCESSING WITH REDUCED REDUNDANCY
Granted: November 14, 2013
Application Number:
20130304943
A method for broadcast forwarding in a SAS topology having a zoned portion of a service delivery system (ZPSDS) is disclosed. The ZPSDS includes at least a first zoning expander and a second zoning expander. The method includes originating a broadcast primitive on the first zoning expander; forwarding solely the broadcast primitive to the second zoning expander from the first zoning expander; initiating a discovery process from the second zoning expander upon receiving the broadcast…
NETWORK RESISTOR MODEL ANALYSIS TOOL
Granted: November 7, 2013
Application Number:
20130298090
The invention may be embodied in a network resistor model analysis tool for an Electrical Rule Checking (ERC) system. The network resistor model analysis tool typically includes, but need not be limited to, (i) a recursive, deterministic resistor path algorithm that identifies all valid resistor paths from a start net to a stopping net in a netlist corresponding to an analog circuit, (ii) a programming representation algorithm complete for representing the resistor paths in a…
LOW-DENSITY PARITY-CHECK DECODER DISPARITY PREPROCESSING
Granted: November 7, 2013
Application Number:
20130297988
Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level…
ZERO-ONE BALANCE MANAGEMENT IN A SOLID-STATE DISK CONTROLLER
Granted: November 7, 2013
Application Number:
20130297986
An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the…
SCAN TEST CIRCUITRY WITH SELECTABLE TRANSITION LAUNCH MODE
Granted: October 31, 2013
Application Number:
20130290799
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises transition launch mode selection circuitry configured to provide independent selection between multiple transition launch modes for each of a plurality of clock domains of the integrated circuit. The multiple transition launch modes may…
MELTHODS AND SYSTEMS FOR INSTANTANEOUS ONLINE CAPACITY EXPANSION
Granted: October 31, 2013
Application Number:
20130290626
The disclosure provides instantaneous, vertical online capacity expansion (OCE) for redundant (e.g., RAID-5, RAID-6) and non-redundant (e.g., RAID-0) arrays. The new OCE technique implements vertical expansion instead of the horizontal expansion techniques implemented in current OCE techniques. The vertical expansion treats any new addition of storage as an extension of the capacity of the preexisting physical drives in order to avoid having to rewrite the data blocks of the original,…
HIGHER-LEVEL REDUNDANCY INFORMATION COMPUTATION
Granted: October 31, 2013
Application Number:
20130290618
Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the…
LINUX I/O SCHEDULER FOR SOLID-STATE DRIVES
Granted: October 31, 2013
Application Number:
20130290601
An I/O scheduler and a method for scheduling I/O requests to a solid-state drive (SSD) is disclosed. The I/O scheduler in accordance with the present disclosure bundles the write requests in such a form that the write requests in each bundle goes into one SSD block. Bundling the write requests in accordance with the present disclosure reduces write amplification and increases system performance. The I/O scheduler in accordance with the present disclosure also helps increasing the life of…
Interconnect Congestion Reduction for Memory-Mapped Peripherals
Granted: October 31, 2013
Application Number:
20130290582
A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus…
METHODS AND STRUCTURE FOR DETERMINING MAPPING INFORMATION INCONSISTENCIES IN I/O REQUESTS GENERATED FOR FAST PATH CIRCUITS OF A STORAGE CONTROLLER
Granted: October 31, 2013
Application Number:
20130290571
Methods and structure are disclosed for improved processing of fast path I/O requests in a storage controller utilizing version information embedded in the fast path I/O requests. The version information allows the storage controller to determine if the mapping information utilized by the host system in generating a fast path I/O request specifies the mapping information utilized by the storage controller. The controller comprises a fast path I/O request processing circuit tightly…
METHODS AND STRUCTURE FOR IDENTIFYING SUPPORT FOR SUPER-STANDARD FEATURES IN COMMUNICATIONS BETWEEN SERIAL ATTACHED SCSI DEVICES
Granted: October 31, 2013
Application Number:
20130290570
Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents…
INTER-TRACK INTERFERENCE MITIGATION IN MAGNETIC RECORDING SYSTEMS USING AVERAGED VALUES
Granted: October 31, 2013
Application Number:
20130286498
Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems using averaged values. Inter-track interference (ITI) is mitigated in a magnetic recording system by obtaining ITI cancellation data; and providing the ITI cancellation data for ITI mitigation, wherein the ITI mitigation is performed in combination with an averaging procedure for one or more of ITI mitigation of averaged data and averaging of ITI mitigated data. The…
MULTI-LAYER INTEGRATED TRANSMISSION LINE CIRCUITS HAVING IMPROVED SIGNAL LOSS CHARACTERISTICS
Granted: October 31, 2013
Application Number:
20130285769
Multi-layer in integrated transmission line circuits are provided having improved signal loss characteristics. A multi-layer integrated transmission line circuit, such as a stripline circuit or a microstrip circuit, comprises at least one reference layer; at least one conducting layer having one or more conducting strips, wherein the at least one conducting layer is separated from the at least one reference layer by a substrate; and at least one additional layer positioned between the at…
INTEGRATED CIRCUIT POWER GRID WITH IMPROVED ROUTING RESOURCES AND BYPASS CAPACITANCE
Granted: October 31, 2013
Application Number:
20130285219
An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal…
CHUNK-BASED DOUBLE-DWELL PREAMBLE DETECTION
Granted: October 24, 2013
Application Number:
20130279404
In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data…
