Method and Apparatus to Perform Floating Point Operations
Granted: October 24, 2013
Application Number:
20130282780
A method of subtracting floating-point numbers includes determining whether a first sign associated with a first floating-point number is unequal to a second sign associated with a second floating-point number, determining whether a first exponent associated with the first floating-point number is less than a second exponent associated with the second floating-point number, negating a first mantissa associated with the first floating-point number when the first sign is unequal to the…
METHODS AND STRUCTURE FOR LUN MASKING IN A SWITCHING DEVICE
Granted: October 24, 2013
Application Number:
20130282978
Methods and structure for masking of logical unit numbers (LUNs) within a switching device coupled with one or more storage enclosures. Each storage enclosure defines one or more logical volumes each identified by a LUN within the storage enclosures. The switching device gathers LUN definition information regarding each LUN defined by each storage enclosure coupled with the switching device. LUN access permission information may be provided by an administrative node/user defining a level…
METHOD FOR SELECTIVE REPLICATION OF PHYSICAL DEVICES ON A VIRTUAL SELF-CONFIGURING ZONING EXPANDER
Granted: October 24, 2013
Application Number:
20130283264
Disclosed is a method and SAS controller that abstract access from virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical…
TREND-ANALYSIS SCHEME FOR RELIABLY READING DATA VALUES FROM MEMORY
Granted: October 17, 2013
Application Number:
20130275843
In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of…
SCAN-BASED CAPTURE AND SHIFT OF INTERFACE FUNCTIONAL SIGNAL VALUES IN CONJUNCTION WITH BUILT-IN SELF-TEST
Granted: October 17, 2013
Application Number:
20130275824
An integrated circuit comprises a memory or other type of circuit core having an input interface and an output interface, built-in self-test circuitry configured for testing of the circuit core between its input and output interfaces in a built-in self-test mode of operation, and at least one scan chain having a plurality of scan cells. The scan cells of the scan chain are coupled to respective signal lines at the input and output interfaces and configured to allow capture of functional…
SSD CACHE EXPANSION USING OVERPROVISIONED SPACE
Granted: October 17, 2013
Application Number:
20130275672
The invention provides for SSD cache expansion by assigning all excess overprovisioned space (OP) above a level of advertised SSD memory to SSD cache. As additional SSD memory is needed to provide the advertised SSD memory, an offsetting portion of the OP is reassigned from excess overprovisioned space to the SSD cache. In this manner, the advertised SSD memory is maintained while continuously allocating all available excess OP to cache. The result is that all of the available SSD memory…
METHODS AND STRUCTURE FOR TRANSFERRING ADDITIONAL PARAMETERS THROUGH A COMMUNICATION INTERFACE WITH LIMITED PARAMETER PASSING FEATURES
Granted: October 17, 2013
Application Number:
20130275652
Methods and structure for transferring additional parameters through a communication interface with limited parameter passing features. Features and aspects hereof provide for generating and transmitting multiple related commands from an initiator device to a target device where one or more initial commands provide additional parameters. The additional parameters are utilized in processing the last of the multiple commands to actually perform a desired data transfer. The initial commands…
METHODS FOR EXCHANGING ADMINSITRATIVE INFORMATION THROUGH A COMMUNICATION INTERFACE WITH LIMITED ADMINISTRATIVE INFORMATION EXCHANGE FEATURES
Granted: October 17, 2013
Application Number:
20130275627
Methods and structure for transferring administrative information through a communication interface. Features and aspects hereof provide for exchanging administrative information between an initiator device and a target device using read and write commands encoded with a reserved sub-tag value. In the context of a Serial Advanced Technology Attachment (SATA) system, a portion of a parameter (e.g., the LBA parameter) of a read or write command (a Native Command Queuing command) is defined…
MEMORY DEVICE HAVING MULTI-PORT MEMORY CELL WITH EXPANDABLE PORT CONFIGURATION
Granted: October 17, 2013
Application Number:
20130272076
A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down…
STORAGE DEVICE HAVING DEGAUSS CIRCUITRY WITH SEPARATE CONTROL OF DEGAUSS SIGNAL STEADY STATE AND OVERSHOOT PORTIONS
Granted: October 17, 2013
Application Number:
20130271867
A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and…
METHODS AND APPARATUS FOR EFFICIENT TONE DETECTION
Granted: October 10, 2013
Application Number:
20130268571
An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a…
ON-CHIP INTEGRATED CIRCUIT POWER MEASUREMENT CELL
Granted: October 10, 2013
Application Number:
20130268221
A power measurement cell, or group of power measurement cells, for the calculation of the power consumption of one or more electrical signals, as well as monitoring electrical signals in an integrated circuit, are disclosed. Further, super cells for the automation of specialized functions associated with the calculation of power consumption of one or more electrical signals are also disclosed. Methods associated with the use of the one or more power measurement cells and for the use of…
Proxy Responder for Handling Anomalies in a Hardware System
Granted: October 3, 2013
Application Number:
20130262918
An apparatus for handling anomalies in a hardware system including a master device and at least one slave device coupled with the master device through an interconnect device is provided. The apparatus includes at least one controller operative to receive status information relating to the slave device. The status information is indicative of whether an anomaly is present in the slave device and/or the interconnect device. The controller is operative to generate output response…
ON-DEMAND ALLOCATION OF CACHE MEMORY FOR USE AS A PRESET BUFFER
Granted: October 3, 2013
Application Number:
20130262772
A data processing system comprises data processing circuitry, a cache memory, and memory access circuitry. The memory access circuitry is operative to assign a memory address region to be allocated in the cache memory with a predefined initialization value. Subsequently, a portion of the cache memory is allocated to the assigned memory address region only after the data processing circuitry first attempts to perform a memory access on a memory address within the assigned memory address…
FILE SYSTEM HINTING
Granted: October 3, 2013
Application Number:
20130262533
A method for generating and communicating file system hints. The method may include receiving an I/O request from a file system layer and checking the I/O request for file system contextual information. The method may also include accessing the file system layer to determine attributes of the file system contextual information and receiving the attributes of the file system contextual information from the file system layer. The method may further include analyzing attributes of the file…
SCATTER GATHER LIST FOR DATA INTEGRITY
Granted: October 3, 2013
Application Number:
20130262398
A system and method for improving message passing between a computer and peripheral devices is disclosed. The system and method for improving message passing between a computer and peripheral devices incorporate data checking on the command/message data and each scatter gather list element. The method in accordance with the present disclosure enables a peripheral device to check the integrity of the message and ownership of the scatter gather list element before the data is processed.
MULTI-PROTOCOL BRIDGE WITH INTEGRATED PERFORMANCE ACCELERATING CACHE
Granted: October 3, 2013
Application Number:
20130259062
A protocol bridge includes a cache for caching data from a plurality of data storage devices, and for servicing data requests from a plurality of initiators. Data is cached for every data access operation such that the most frequently accessed data remains replicated in the cache.
MEMORY DEVICE HAVING CONTROL CIRCUITRY FOR SENSE AMPLIFIER REACTION TIME TRACKING
Granted: October 3, 2013
Application Number:
20130258794
A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to the memory array. The sensing circuitry comprises a plurality of output sense amplifiers configured to sense stored data associated with respective columns of the memory array, and sense amplifier control circuitry configured to generate a sense amplifier control signal for application to control inputs of respective ones of the output sense…
Victim Port-Based Design for Test Area Overhead Reduction in Multiport Latch-Based Memories
Granted: October 3, 2013
Application Number:
20130258786
A multiport latch-based memory device includes a latch array, a plurality of first multiplexers, and a second multiplexer. The latch array is responsive to output data from an input data register in a functional mode associated with the latch-based memory device. The plurality of first multiplexers is responsive to output data from the latch array in the functional mode. The plurality of first multiplexers is responsive to output data from the input data register in a test mode…
Adaptive Voltage Scaling Using a Serial Interface
Granted: September 26, 2013
Application Number:
20130249290
An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on…
