SENDING FAILURE INFORMATION FROM A SOLID STATE DRIVE (SSD) TO A HOST DEVICE
Granted: September 26, 2013
Application Number:
20130254597
A system, method, and computer program product are provided for sending failure information from a solid state drive (SSD) to a host device. In operation, an error is detected during an operation associated with a solid state drive. Additionally, a command is received for failure information from a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure information associated with the solid state…
METHODS AND STRUCTURE FOR RAPID OFFLOADING OF CACHED DATA IN A VOLATILE CACHE MEMORY OF A STORAGE CONTROLLER TO A NONVOLATILE MEMORY
Granted: September 26, 2013
Application Number:
20130254457
Methods and structure for rapid offloading of cached data in a volatile cache memory of a storage controller to a nonvolatile memory. Features and aspects hereof provide an enhanced storage controller having a volatile cache memory and multiple communication channels each coupled with a corresponding nonvolatile memory device. Responsive to detecting an impending loss of power, control logic of the controller copies data from the volatile cache memory to the multiple nonvolatile memories…
Variable Node Processing Unit
Granted: September 26, 2013
Application Number:
20130254252
A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are…
Phase Alignment Between Phase-Skewed Clock Domains
Granted: September 26, 2013
Application Number:
20130251007
In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one…
BASE STATION TIMING CONTROL USING SYNCHRONOUS TRANSPORT SIGNALS
Granted: September 26, 2013
Application Number:
20130250850
A base station of a wireless system comprises a local clock source and timing circuitry coupled to the local clock source. The timing circuitry is configured to adjust at least one parameter of the local clock source based at least in part on timing information extracted from designated portions of each of one or more frames of a synchronous transport signal received in the base station. The base station may further comprise a physical layer device, such as a mapper, configured to…
SYSTEM AND METHOD FOR DECREASING SIGNAL INTEGRITY NOISE BY USING VARYING DRIVE STRENGTHS BASED ON LIKELIHOOD OF SIGNALS BECOMING VICTIMS
Granted: September 26, 2013
Application Number:
20130249591
A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.
ADAPTIVE FILTER WITH COEFFICIENT DETERMINATION BASED ON OUTPUT OF REAL TIME CLOCK
Granted: September 19, 2013
Application Number:
20130243050
A transceiver comprises a transmitter and a receiver. At least one of the transmitter and the receiver comprises an adaptive filer. One or more coefficients of the adaptive filter are determined based at least in part on an output of a real time clock. The adaptive filter may comprise a coefficient update engine and a memory for storing a plurality of sets of adaptive filter coefficients in association with respective time indicators derived from the output of the real time clock, with…
Systems and Methods for Out of Order Processing in a Data Retry
Granted: September 19, 2013
Application Number:
20130246888
Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order.
DYNAMIC HIGHER-LEVEL REDUNDANCY MODE MANAGEMENT WITH INDEPENDENT SILICON ELEMENTS
Granted: September 19, 2013
Application Number:
20130246839
A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned…
SAS EXPANDER AND METHOD TO ARBITRATE TRAFFIC IN A REDUNDANT EXPANDER SYSTEM
Granted: September 19, 2013
Application Number:
20130246671
A SAS expander configured to operate as a SAS expander hub receives IO requests from connected SAS expanders and relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.
METHODS AND APPARATUS FOR PACKING RECEIVED FRAMES IN BUFFERS IN A SERIAL ATTACHED SCSI (SAS) DEVICE
Granted: September 12, 2013
Application Number:
20130238821
Methods and apparatus for packing received Serial Attached SCSI (SAS) frames in buffers for transmission to a host system memory. SAS frames are received from another SAS device and stored in a frame buffer memory. User data in the received frames has appended SCSI Data Integrity Fields (DIF information) to enhance reliability. Features and aspects hereof use the DIF information to validate the user data and then strip the DIF information to densely pack the validated user data in a DMA…
Optimization of Data Processors with Irregular Patterns
Granted: September 12, 2013
Application Number:
20130235907
In described embodiments, data streams with irregular patterns are processed by transformations defined by recursively changing processor state, or iteration level. The data transformations are applied to an arbitrary long portion of data, instead of small portions, that are defined directly by a current processor state. Embodiments combine small parts of, for example, puncturing/repetition patterns into a pattern of bigger parts and apply these patterns of bigger parts to relatively…
ANALOG TUNNELING CURRENT SENSORS FOR USE WITH DISK DRIVE STORAGE DEVICES
Granted: September 12, 2013
Application Number:
20130235487
Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier,…
STORAGE DEVICE HAVING WRITE SIGNAL WITH MULTIPLE-SLOPE DATA TRANSITION
Granted: September 12, 2013
Application Number:
20130235485
A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to or otherwise associated with the read/write head. The control circuitry comprises a write driver configured to generate a write signal for data to be written to the storage disk, and a multiple-slope transition controller associated with the write driver and configured to control a data transition in the…
Multi-Path Data Processing System
Granted: September 12, 2013
Application Number:
20130235484
Various embodiments of the present invention provide apparatuses and methods for processing data in a multi-path data processing circuit. For example, an apparatus is disclosed that includes a first filter operable to process a first digital data stream to yield a first filtered digital data stream, a second filter operable to process a second digital data stream to yield a second filtered digital data stream, wherein the first and second digital data stream are representative of a same…
Digital-to-Analog Converter
Granted: September 12, 2013
Application Number:
20130234874
A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain…
Data Processing System with Thermal Control
Granted: September 5, 2013
Application Number:
20130232360
Various embodiments of the present invention provide systems and methods for a data processing system with thermal control. For example, a data processing system with thermal control is disclosed that includes a number of data processors and a scheduler, which is operable to determine the power consumption of the data processors and to switch the data processing system from a first mode to a second mode and from the second mode to a third mode. The data processing system consumes less…
METHOD FOR OPTIMIZING WIDE PORT POWER MANAGEMENT IN A SAS TOPOLOGY
Granted: September 5, 2013
Application Number:
20130232281
A SAS expander or initiator places PHYs in a wide port into a persistent reduced power state by signaling to the connected SAS device that the SAS expander or initiator intends to route data traffic through other PHYs in the wide port. The SAS expander or initiator and connected SAS device agree to disuse certain PHYs so that the PHYs enter a reduced power state according to SAS standards.
ACTIVE BACK UP AUTO CHANGEOVER VOLTAGE BUS
Granted: August 29, 2013
Application Number:
20130221750
Several methods and a system to implement an efficient power supply management are disclosed. In one embodiment, an apparatus of a voltage supply includes a power supply providing a voltage. The apparatus includes an active supply module communicating with a supply voltage to a voltage bus through an ORing element. The apparatus also includes a redundant supply module providing an additional voltage to the voltage bus if the active supply module fails, through an additional ORing…
DIGITAL PHASE LOCKED LOOP
Granted: August 29, 2013
Application Number:
20130222026
An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock…
