INTEGRATED CIRCUIT HAVING CLOCK GATING CIRCUITRY RESPONSIVE TO SCAN SHIFT CONTROL SIGNAL
Granted: August 22, 2013
Application Number:
20130219238
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock…
Data Integrity Field (DIF) Implementation with Error Detection and Intelligent Recovery Mechanism
Granted: August 22, 2013
Application Number:
20130219234
An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a…
ACCELERATED REBUILD AND ZERO TIME REBUILD IN RAID SYSTEMS
Granted: August 22, 2013
Application Number:
20130219214
A RAID data storage system incorporates permanently empty blocks into each stripe, distributed among all the data storage devices, to accelerate rebuild time by reducing the number of blocks that need to be rebuilt in the event of a failure.
CONFIGURABLE PRIORITIZATION OF DATA TRANSMISSION IN A DATA STORAGE TOPOLOGY
Granted: August 22, 2013
Application Number:
20130219088
Processing input/output requests may include: processing one or more input/output (IO) requests in a first IO queue associated with a first device group; detecting a queuing of one or more IO requests in a second IO queue associated with a second device group; pausing the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a detection of a queuing of one or more IO requests in a second IO queue associated with a second device…
MEMORY DEVICE HAVING SENSING CIRCUITRY WITH AUTOMATIC LATCHING OF SENSE AMPLIFIER OUTPUT NODE
Granted: August 22, 2013
Application Number:
20130215685
A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to bitlines associated with respective columns of the memory cells of the memory array. The sensing circuitry comprises, for at least a given one of the bitlines of the memory array, a sense amplifier configured to sense data on the given bitline, with the sense amplifier having at least one internal node and at least one output node. The sensing…
METHOD FOR ROBUST PREAMBLE LOCATION IN A DQS SIGNAL
Granted: August 15, 2013
Application Number:
20130208553
A method for robust preamble location and gate training in a Double Data Rate type Three (DDR3) computing environment. A single algorithm is employed to begin sampling a Data Strobe Signal (DQS) at a maximum delay value designed to fall within the driven region of a DQS. The method then begins sampling the DQS in a sequence of delay values from right to left. Each result of the sampling indicating a high state and a low state are stored as well as the occasions where the DQS transitioned…
DISK-BASED STORAGE DEVICE WITH HEAD POSITION CONTROL RESPONSIVE TO DETECTED INTER-TRACK INTERFERENCE
Granted: August 8, 2013
Application Number:
20130201579
A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises an inter-track interference detector configured to process a signal read from at…
METHODS AND SYSTEMS FOR TWO DEVICE FAILURE TOLERANCE IN A RAID 5 STORAGE SYSTEM
Granted: August 8, 2013
Application Number:
20130205167
Methods and systems for two device failure tolerance in a RAID 5 storage system. Features and aspects hereof provide for allocating a spare storage device in the storage system for use with a standard RAID level 5 storage volume to form an enhanced RAID level 5 volume. Additional redundancy information is generated and stored on the spare storage device such that the enhanced RAID level 5 volume is operated by the storage controller so as to survive a failure of up to two of the storage…
SYSTEM AND METHOD FOR IMPROVED REBUILD IN RAID
Granted: August 8, 2013
Application Number:
20130205166
The present disclosure is a system and method for improved RAID rebuilds under host IO conditions, that greatly improves rebuild times and prevents host IO starvation. A queue in a drive that is part of the RAID is used to store rebuild and host IO requests, with rebuild IOs issued to the head of the drive queue. Rebuild requests in the drive are delayed by a delay time. This delay ensures there is no unintended side effect of this invention that may result in host IO starvation for the…
METHODS AND STRUCTURE FOR AN IMPROVED SOLID-STATE DRIVE FOR USE IN CACHING APPLICATIONS
Granted: August 8, 2013
Application Number:
20130205065
Methods and structure for an improved solid-state drive (SSD) for use in caching applications. An improved SSD comprises both volatile and non-volatile memory. The volatile memory provides improved performance as compared to present SSDs for use in caching application. The improved SSD senses impending failure of external power applied to the SSD and, while adequate power remains, copies cached data from the volatile memory to the non-volatile memory to retain the data through the power…
REFERENCE VOLTAGE CIRCUIT FOR ADAPTIVE POWER SUPPLY
Granted: August 8, 2013
Application Number:
20130201578
Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example,…
STORAGE DEVICE HAVING CALIBRATION CIRCUITRY PROVIDING PROGRAMMABLE PHASE UPDATE VALUES
Granted: August 8, 2013
Application Number:
20130201576
A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises calibration circuitry configured to vary a phase of a clock signal as a test pattern is written to the storage disk as part of a calibration procedure, and disk locked…
UPDATE SYSTEMS RESPONSIVE TO ONGOING PROCESSING AT A STORAGE SYSTEM
Granted: August 1, 2013
Application Number:
20130198730
Methods and systems for updating devices of a storage system are provided. The system comprises a management system and at least one client system. The management system contacts a network-accessible portal providing updates for firmware residing on storage system devices. The client system is coupled for communication with the management system and comprises one or more storage system devices. The management system acquires version information for the storage system devices of the…
Method and Apparatus for Debugging System-on-Chip Devices
Granted: August 1, 2013
Application Number:
20130198566
A device that provides debug mode information associated with a System-on-Chip (SoC) device includes a multiplexer, debug controller, and a memory device internal to the SoC device and coupled to the multiplexer. The multiplexer directs debug mode information to the memory device in response to the SoC device being in a debug mode. The debug controller stores the debug mode information in the memory device in response to a triggering signal, and the triggering signal is associated with a…
SYSTEMS AND METHODS FOR STORAGE PROTOCOL COMPLIANCE TESTING
Granted: August 1, 2013
Application Number:
20130198423
Methods and devices are provided for determining compliance with standards for at least one of Serial Attached SCSI and Serial Advanced Technology Attachment (SAS/SATA). The device comprises PHY layer logic operable to couple the device with another device, and a control unit. The control unit is operable to direct operations of the PHY layer logic, and to determine that the other device is a SAS/SATA device. The control unit is further operable to perform SAS/SATA protocol compliance…
TABLE-BASED RESOURCE MAPPING FOR DOWNLINK CONTROL CHANNELS IN A WIRELESS SYSTEM BASE STATION
Granted: August 1, 2013
Application Number:
20130195021
A transmitter comprises resource mapping circuitry configured to map symbols from multiple control channels to transmission symbols in a base station of a wireless system. The resource mapping circuitry comprises a table-based mapper configured to receive the control channel symbols and to map those symbols to the transmission symbols utilizing at least a selected one of a plurality of tables providing respective distinct mappings between the control channel symbols and the transmission…
INCREMENTAL PREAMBLE DETECTION
Granted: August 1, 2013
Application Number:
20130195007
In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile…
DOWNLINK INDICATOR CHANNEL PROCESSING IN A WIRELESS SYSTEM BASE STATION
Granted: July 25, 2013
Application Number:
20130188553
A transmitter comprises indicator channel processing circuitry configured to process indicator channel codewords for transmission in a base station of a wireless system. The indicator channel processing circuitry performs a plurality of processing operations on the indicator channel codewords in a specified processing sequence, with the plurality of processing operations comprising at least modulation, scrambling, spreading and combining. In the specified processing sequence, the…
Systems and Methods for Dynamic Scaling in a Data Decoding System
Granted: July 25, 2013
Application Number:
20130191618
Various embodiments of the present invention provide systems and methods for data processing using variable scaling.
METHODS AND SYSTEMS FOR REDUCED SIGNAL PATH COUNT FOR INTERCONNECT SIGNALS WITHIN A STORAGE SYSTEM EXPANDER
Granted: July 25, 2013
Application Number:
20130191573
Methods and systems for reducing the signal path count between circuits within a SAS expander used for establishing SAS connections. The system comprises a SAS expander. The SAS expander comprises a plurality of link layer control circuits, each link layer control circuit adapted to communicatively couple with a SAS device. The SAS expander further comprises a connection manager communicatively coupled with the link layer control circuits for routing communications between the link layer…
