Method and Apparatus for Decreasing Leakage Power Consumption in Power Gated Memories
Granted: July 25, 2013
Application Number:
20130191665
A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select…
SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A MULTI-SEGMENT SCAN CHAIN
Granted: July 18, 2013
Application Number:
20130185607
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively…
DETECTION AND DECODING IN FLASH MEMORIES USING CORRELATION OF NEIGHBORING BITS
Granted: July 18, 2013
Application Number:
20130185599
Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a given page of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value for a bit among said plurality of bits based on a probability that a data pattern was written to the…
APPLICATION OF ALTERNATE ALIGN PRIMITIVES DURING SAS RATE MATCHING TO IMPROVE CONTINUOUS ADAPTATION
Granted: July 18, 2013
Application Number:
20130185466
The present invention is directed to a method which allows for substitution of standard SAS ALIGN primitives with an alternative, more spectrally pure set of SAS ALIGN primitives that allows for enhanced continuous adaptation performance. Two consenting SAS devices which are connected to each other may negotiate for and start communicating using the alternate set of ALIGN primitives, which may allow for improved jitter tolerance and reduced bit error rate.
CODING CIRCUITRY FOR DIFFERENCE-BASED DATA TRANSFORMATION
Granted: July 18, 2013
Application Number:
20130181852
Coding circuitry for difference-based data transformation in an illustrative embodiment comprises a difference-based encoder having a plurality of processing stages, with the difference-based encoder being configured to generate respective orders of difference from a sequence of data samples and to output encoded data determined based on at least a selected one of the orders of difference. The coding circuitry may be configured to implement lossless, linear compression of the sequence of…
INTER-CELL INTERFERENCE CANCELLATION IN FLASH MEMORIES
Granted: July 11, 2013
Application Number:
20130176779
Inter-cell interference cancellation is provided for flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized threshold voltage values for at least one target cell of the flash memory device; obtaining one or more hard decision read values for at least one aggressor cell of the target cell; determining an aggressor state of the at least one aggressor cell; determining an interference amount based on the aggressor state; determining an…
SCAN CHAIN LOCKUP LATCH WITH DATA INPUT CONTROL RESPONSIVE TO SCAN ENABLE SIGNAL
Granted: July 11, 2013
Application Number:
20130179742
A scan chain lockup latch comprises at least one latching element and data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal. The lockup latch is configured for coupling between first and second scan cells of a scan chain. The scan chain may be controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal. The data input control…
MAPPING CIRCUIT TEST LOGIC BY ANALYZING REGISTER TRANSFER LEVEL CIRCUIT MODELS
Granted: July 11, 2013
Application Number:
20130179741
Methods and systems for mapping and programming the debug logic of a circuit are provided. The system acquires a Register Transfer Level (RTL) representation of a circuit, wherein the circuit implements test logic that is externally programmable for providing one or more output signals corresponding to internal operational signals. The system analyzes the RTL representation to identify test multiplexers (MUXs) having registers for implementing the test logic, and correlates test register…
SYSTEMS AND METHODS FOR IDLE TIME BACKUP OF STORAGE SYSTEM VOLUMES
Granted: July 11, 2013
Application Number:
20130179634
Methods and systems for backing up data of a RAID 0 volume. The system includes a plurality of storage devices implementing a logical volume in a Redundant Array of Independent Disks (RAID) level 0 configuration. The system also includes a storage controller. The storage controller is adapted to manage Input/Output (I/O) operations directed to the RAID 0 volume. The storage controller is further adapted to duplicate data stored on the RAID 0 volume to unused portions of other storage…
DETECTION AND DECODING IN FLASH MEMORIES WITH ERROR CORRELATIONS FOR A PLURALITY OF BITS WITHIN A SLIDING WINDOW
Granted: July 11, 2013
Application Number:
20130176780
Methods and apparatus are provided for detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of…
CELL-LEVEL STATISTICS COLLECTION FOR DETECTION AND DECODING IN FLASH MEMORIES
Granted: July 11, 2013
Application Number:
20130176778
Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level…
Scan Test Circuitry with Delay Defect Bypass Functionality
Granted: July 4, 2013
Application Number:
20130173976
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be…
POWER SWITCH HAVING SERIES-CONNECTED SWITCHING STAGES
Granted: July 4, 2013
Application Number:
20130173077
A power switch of a processing device comprises a plurality of series-connected switching stages, with each switching stage comprising a plurality of parallel-connected switching devices and an inverter chain. The switching devices are coupled between a power supply input and a power supply output of the power switch. Each of the switching devices of a given one of the switching stages is driven by an output of a corresponding one of the inverters of the inverter chain of that stage. A…
Biquad Infinite Impulse Response System Transformation
Granted: July 4, 2013
Application Number:
20130170585
A BIIR system includes a first delay line for receiving at least one input data sample and generating delayed input samples as a function of the input data sample. The BIIR system further includes a second delay line including multiple delay elements connected in series for generating delayed output samples. An input of one of the delay elements receives at least one output data sample of the BIIR system. A summation element in the BIIR system generates the output data sample of the BIIR…
Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers
Granted: July 4, 2013
Application Number:
20130170273
A CAM circuit includes a plurality of core memory cells, each cell including comparison logic for generating a local match signal based on a comparison between stored data in the cell and a compare value. The CAM circuit includes a plurality of local match lines, each local match line coupled with a corresponding cell and adapted to convey the local match signal generated by the cell. The CAM circuit includes combination logic for receiving respective local match signals generated by a…
METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE
Granted: July 4, 2013
Application Number:
20130167895
A device and method wherein a thermo electric generator device is disposed between stacks of a multiple level device, or is provided on or under a die of a package and is conductively connected to the package. The thermo electric generator device is configured to generate a voltage by converting heat into electric power. The voltage which is generated by the thermo electric generator can be recycled back into the die itself, or to a higher-level unit in the system, even to a cooling fan.
INTEGRATED CIRCUIT (IC) LEADFRAME DESIGN
Granted: June 27, 2013
Application Number:
20130161805
Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge, the at least one edge having one or more slots located therein. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of pairs of adjacent lead fingers extend into corresponding…
ARBITRATION CIRCUITRY FOR ASYNCHRONOUS MEMORY ACCESSES
Granted: June 27, 2013
Application Number:
20130166938
A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in…
METHODS AND STRUCTURE FOR COMMUNICATING BETWEEN A SATA HOST AND A SATA TARGET DEVICE THROUGH A SAS DOMAIN
Granted: June 27, 2013
Application Number:
20130166811
Methods and structure for directly coupling SATA hosts (SATA initiators) with SATA target devices through a SAS fabric and an enhanced SAS expander supporting such direct couplings. The enhanced SAS expander comprises SATA/STP connection logic to open a SAS (STP) connection between a directly attached SATA host and a SATA target device in response to receipt of an FIS from the host or target while no connection is presently open. The opened connection is closed after expiration of a…
REFRAMING CIRCUITRY WITH VIRTUAL CONTAINER DROP AND INSERT FUNCTIONALITY TO SUPPORT CIRCUIT EMULATION PROTOCOLS
Granted: June 27, 2013
Application Number:
20130163612
Reframing circuitry controls communications between a physical layer device and a link layer device. In a first direction of communication, the reframing circuitry receives a container frame with the container frame having a first arrangement of columns, and outputs a virtual container frame that includes a modified version of the container frame received by the reframing circuitry, with the modified version of the container frame having a second arrangement of columns different than the…
