LOCATION AND TIMING WINDOW BASED DECOUPLING CAPACITOR EVAULATION TOOL AND METHOD
Granted: June 27, 2013
Application Number:
20130167096
A method of designing an integrated circuit includes receiving a placement database of logic devices of an electronic device design that includes first and second logic devices. The method further includes determining a first timing window associated with a first state transition of the first logic device, and a second timing window associated with a second state transition of the second logic device. In the event that the first and second timing windows overlap, the placement database…
CHAINED, SCALABLE STORAGE DEVICES
Granted: June 20, 2013
Application Number:
20130159622
Described embodiments access data in a chained, scalable storage system. A primary agent of one or more storage devices receives a host request including a logical address from a host coupled to the primary agent. The primary agent determines, based on the logical address, a corresponding physical address in at least one of the storage devices and generates, based on the physical address, a sub-request for each determined physical address in the storage devices. The primary agent sends,…
Method and Apparatus for Calculating an N-Point Discrete Fourier Transform
Granted: June 20, 2013
Application Number:
20130159368
Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least…
Implementation of Negation in a Multiplication Operation Without Post-Incrementation
Granted: June 20, 2013
Application Number:
20130159367
A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to…
TRAINING AN ECHO CANCELLER IN SEVERE NOISE
Granted: June 20, 2013
Application Number:
20130156210
An apparatus includes a non-adaptive filter, an adaptive filter, and a controller. The non-adaptive filter may have non-adaptive filter coefficients and be configured to develop a non-adaptive error signal as a function of the non-adaptive filter coefficients. The adaptive filter may have adaptive filter coefficients and be configured to develop an adaptive error signal as a function of the adaptive filter coefficients. The controller may be configured to monitor a quality of the…
METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE
Granted: June 20, 2013
Application Number:
20130154109
The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region…
SOLDER INTERCONNECT BY ADDITION OF COPPER
Granted: June 13, 2013
Application Number:
20130149857
A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.
OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
Granted: June 13, 2013
Application Number:
20130152036
Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.
SYSTEM AND METHOD FOR REDUCING INTEGRATED CIRCUIT TIMING DERATING
Granted: June 13, 2013
Application Number:
20130152034
A system for, and method of, reducing IC timing derating for a path in an integrated circuit design. In one embodiment, the system includes an electronic design automation tool configured to (1) extract circuit data regarding cells in the path and (2) calculate a timing derating for the path based at least in part on a determination as to whether the cells are simple cells.
VIDEO GAME AND METHOD HAVING ENHANCED AUDIO EFFECTS
Granted: June 13, 2013
Application Number:
20130150162
A computer-readable medium, a method of conducting a video game and a gaming system. In one embodiment, the medium contains programming instructions that cause a computer processor to: (1) conduct a video game that generates events having corresponding exclusively audible prompts and (2) convey the exclusively audible prompts to specific audio channels for sound-capable gaming controllers of a gaming system.
Systems and Methods for Medium Proximity Detection in a Read Channel
Granted: June 13, 2013
Application Number:
20130148230
A contact event between a sensing device and a storage medium is detected by receiving a signal indicating a physical proximity between the sensing device and the storage medium; generating a plurality of frequency bin outputs; comparing one or more frequency bin outputs to a corresponding first level threshold to yield a corresponding comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; comparing the…
ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LOW PARITY DENSITY CHECK CODES
Granted: June 6, 2013
Application Number:
20130145238
Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional…
DETECTION AND DECODING IN FLASH MEMORIES WITH SELECTIVE BINARY AND NON-BINARY DECODING
Granted: June 6, 2013
Application Number:
20130145235
Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular…
Method and Apparatus to Reduce a Quantity of Error Detection/Correction Bits in Memory Coupled to a Data-Protected Processor Port
Granted: June 6, 2013
Application Number:
20130145227
An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a…
MELTHOD AND SYSTEM FOR INTEGRATING THE FUNCTIONS OF A CACHE SYSTEM WITH A STORAGE TIERING SYSTEM
Granted: June 6, 2013
Application Number:
20130145095
A tiered data storage system having a cache employs a tiering management subsystem to analyze data access patterns over time, and a cache management subsystem to monitor individual input/output operations and replicate data in the cache. The tiering management subsystem determines a distribution of data between tiers and determines what data should be cached while the cache management subsystem moves data into the cache. The tiered data storage system may analyze individual input/output…
Hierarchical Self-Organizing Classification Processing in a Network Switch
Granted: June 6, 2013
Application Number:
20130142205
Described embodiments process data packets received by a switch coupled to a network processor. The switch determines whether one or more rules for classifying and processing the received packet are stored in an internal classification database of the switch. If one or more rules are stored in the internal database, the switch updates statistics corresponding to each of the rules and classifies and processes the received packet in accordance with the rules. If no associated rules are…
STORAGE DEVICE HAVING CLOCK ADJUSTMENT CIRCUITRY WITH FIRMWARE-BASED PREDICTIVE CORRECTION
Granted: May 30, 2013
Application Number:
20130135766
A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information…
METHOD FOR EMBEDDING A HOST DRIVER WITHIN A DEVICE
Granted: May 30, 2013
Application Number:
20130139184
The present invention is directed to a method of operation of a host system by which the host system obtains a driver necessary for running a device (ex.—peripheral device, such as a USB stick, printer, etc.) connected to the host system in an operating system of the host system. In the method(s) disclosed herein, the driver (ex.—host driver) is embedded within in an on-board memory of the device itself. The host system queries the device to determine if and where within the device…
LDPC Erasure Decoding for Flash Memories
Granted: May 30, 2013
Application Number:
20130139035
A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash…
METHOD AND APPARATUS FOR EXPANDER-BASED DATA DUPLICATION
Granted: May 30, 2013
Application Number:
20130138851
A data-duplicating expander device attachable to a storage topology and a method. The data-duplicating expander device may include a direct-attached SAS expander configured for direct duplication of data from source disks to destination disks by bypassing transfer to or from a host system. The device may include dedicated expander phys and a processor. The device may be configured to receive instructions from an initiator storage-topology-connected device to configure or start a data…
