METHOD TO IMPROVE I/O RELIABILITY ON A DEGRADED WIDE PORT CONNECTION
Granted: May 23, 2013
Application Number:
20130132782
A method and system for controller level identification and isolation of a degraded physical link (PHY) in a serial attached small computer system interface (SA-SCSI) or SAS domain. The method and system uses computer readable code embodied within the controller level of an SAS domain to monitor a plurality of PHY pairs associated as connecting through a wide port. The invention compares a history of PHY pair errors to a tunable timer to determine if PHY errors reach a threshold. Should…
METHOD AND SYSTEM FOR DISTRIBUTING TIERED CACHE PROCESSING ACROSS MULTIPLE PROCESSORS
Granted: May 23, 2013
Application Number:
20130132674
A data storage system having at least one cache and at least two processors balances the load of data access operations by directing certain processes in each data access operation to one of the processors. Each processor may be optimized for its specific processes. One processor may be dedicated to receiving and servicing data access requests; another processor may be dedicated to background tasks and cache management.
METHOD OF OPTIMIZING FLOATING DFE RECEIVER TAPS
Granted: May 23, 2013
Application Number:
20130128946
A method for determining floating tap positions in a DFE of a receiver is disclosed. The method include providing a group of floating taps for the DFE; obtaining a baseline eye opening value for the receiver when the group of floating taps is disabled; providing a plurality of floating tap distribution configurations, each specifying a distribution configuration for the group of floating taps within the DFE; obtaining a plurality of eye opening values for the receiver, each particular…
NETWORK SWITCH WITH EXTERNAL BUFFERING VIA LOOPAROUND PATH
Granted: May 23, 2013
Application Number:
20130128896
Described embodiments process data packets received by a network switch coupled to an external buffering device. The network switch determines a queue of an internal buffer of the network switch associated with a flow of the received packet and determines whether the received packet should be forwarded to the external buffering device. If the received packet should be forwarded to the external buffering device, the network switch sets an external buffering active indicator indicating…
MEMORY DEVICE WITH AREA EFFICIENT POWER GATING CIRCUITRY
Granted: May 23, 2013
Application Number:
20130128676
A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the…
DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTIAL REMAINDER
Granted: May 16, 2013
Application Number:
20130124594
An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages of computation. In determining the quotient in one embodiment, the divider circuitry is configured to estimate a partial remainder for a given one…
Task Backpressure and Deletion in a Multi-Flow Network Processor Architecture
Granted: May 16, 2013
Application Number:
20130125127
Described embodiments generate tasks corresponding to packets received by a network processor. A source processing module sends task messages including a task identifier and a task size to a destination processing module. The destination module receives the task message and determines a queue in which to store the task. Based on a used cache counter of the queue and a number of cache lines for the received task, the destination module determines whether the queue has reached a usage…
Solid-State Disk Manufacturing Self Test
Granted: May 16, 2013
Application Number:
20130124932
A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers…
APPARATUS TO MANAGE EFFICIENT DATA MIGRATION BETWEEN TIERS
Granted: May 16, 2013
Application Number:
20130124780
A data storage system having a slow tier and a fast tier maintains hot data on the fast tier by migrating data from the slow tier to reserve space on the fast tier as data becomes hot over time. The system maintains a reserve space table and performs a mass migration of data from the fast tier to the slow tier. Data migration is frequently unidirectional with data migrating from the slow to the fast tier, reducing overhead during normal operation.
STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING
Granted: May 16, 2013
Application Number:
20130124777
A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush…
RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT
Granted: May 16, 2013
Application Number:
20130124590
In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to…
METHOD FOR COMPLETING WRITE OPERATIONS TO A RAID DRIVE POOL WITH AN ABNORMALLY SLOW DRIVE IN A TIMELY FASHION
Granted: May 9, 2013
Application Number:
20130117603
The present invention is directed to a method for completing a stripe write operation in a timely fashion to a RAID drive pool which includes an abnormally slow drive. For example, the stripe write operation either completes within a required time interval, or an error is provided to the host/initiator which provides an indication to an application that the stripe write operation did not complete.
METHOD FOR IMPLEMENTING PRE-EMPTIVE READ RECONSTRUCTION
Granted: May 9, 2013
Application Number:
20130117525
The present invention is directed to a method for pre-emptive read reconstruction. In the method(s) disclosed herein, when a pre-emptive read reconstruction timer times out, if one or more drive read operations for providing requested stripe read data are still pending; and if stripe read data corresponding to the pending drive read operations may be constructed (ex.—reconstructed) based on the stripe read data received before the expiration of the timer, the pending drive read…
SERVER DIRECT ATTACHED STORAGE SHARED THROUGH VIRTUAL SAS EXPANDERS
Granted: May 9, 2013
Application Number:
20130117485
A data storage system includes a first server including: a first plurality of storage disks configured to store data, and a first host bus adapter including a first processor configured to provide a first virtual expander and a first logic component; and a second server including: a second plurality of storage disks configured to store data, and a second host bus adapter including a second processor configured to provide a second virtual expander and a second logic component, wherein the…
COMBINED RF EQUALIZER AND I/Q IMBALANCE CORRECTION
Granted: May 9, 2013
Application Number:
20130117342
Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF…
RECURSIVE DIGITAL PRE-DISTORTION (DPD)
Granted: May 9, 2013
Application Number:
20130114762
Recursive digital pre-distortion (DPD) techniques are provided. Digital pre-distortion is performed by applying a signal to a recursive system to generate a state vector; providing the state vector as a feedback value to the recursive non-linear system; and applying the state vector to a second function to generate an output signal, wherein at least one of the recursive system and the second function comprise a non-linear function. The recursive non-linear system can be initialized to a…
MULTI-STAGE CREST FACTOR REDUCTION (CFR) FOR MULTI-CHANNEL MULTI-STANDARD RADIO
Granted: May 9, 2013
Application Number:
20130114761
Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of…
CREST FACTOR REDUCTION (CFR) USING ASYMMETRICAL PULSES
Granted: May 9, 2013
Application Number:
20130114652
Crest factor reduction (CFR) techniques are provided using asymmetrical pulses. A crest factor reduction method comprises obtaining one or more data samples; detecting at least one peak in the one or more data samples; performing peak cancellation on the at least one detected peak by applying an asymmetric cancellation pulse to the at least one detected peak: and providing processed versions of the one or more data samples. The asymmetric cancellation pulse is generated, for example, by…
OPTICALLY-BASED CONTROL FOR DEFROSTING SOLAR PANELS
Granted: May 2, 2013
Application Number:
20130105456
A solar energy system comprising a defrosting module. The defrosting module includes a first light sensor configured to be located on a solar panel and to produce a first signal which is proportional to the intensity of sunlight reaching the solar panel. The defrosting module includes a second light sensor configured to be located proximate to the solar panel and configured to produce a second signal which is proportional to the intensity of ambient sunlight in the vicinity of the solar…
Oversampled Data Processing Circuit With Multiple Detectors
Granted: May 2, 2013
Application Number:
20130106637
Various embodiments of the present invention provide apparatuses and methods for processing data in an oversampled data processing circuit with multiple detectors. For example, an apparatus for processing data is disclosed that includes a first analog to digital converter operable to sample a continuous signal at a first sampling phase to yield a first digital output, a second analog to digital converter operable to sample the continuous signal at a second sampling phase to yield a…
