SCAN ENABLE TIMING CONTROL FOR TESTING OF SCAN CELLS
Granted: May 2, 2013
Application Number:
20130111286
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan enable timing control circuitry coupled between a scan enable input of the scan test circuitry and scan enable inputs of respective ones of the scan cells. The scan enable timing control circuitry is operative to control…
SCAN TEST CIRCUITRY COMPRISING SCAN CELLS WITH FUNCTIONAL OUTPUT MULTIPLEXING
Granted: May 2, 2013
Application Number:
20130111285
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of…
METHODS AND APPARATUS FOR INCREASING DEVICE ACCESS PERFORMANCE IN DATA PROCESSING SYSTEMS
Granted: May 2, 2013
Application Number:
20130111181
A data processing system comprises a device and device access circuitry. The device is mapped to a first mapped address region and to a second mapped address region. The device access circuitry, in turn, is operative to access the device in accordance with a first set of memory attributes when addressing the device within the first mapped address region and to access the device in accordance with a second set of memory attributes when addressing the device within the second mapped…
METHODS AND APPARATUS FOR VALIDATING DETECTION OF RRO ADDRESS MARKS
Granted: May 2, 2013
Application Number:
20130107687
Methods and apparatus are provided for validating a detection of RRO address marks. After a potential RRO address mark is detected, a disclosed RROAM validation metric evaluates the energy of the remaining RRO data bits in the servo sector, relative to a predefined energy threshold. In addition, the number of remaining RRO data bits in the servo sector is compared to an expected value. The detected RRO address mark is validated in an exemplary embodiment if the RROAM validation metric…
DIGITAL INPUT DETECTOR AND ASSOCIATED ADAPTIVE POWER SUPPLY
Granted: May 2, 2013
Application Number:
20130107392
Interface circuitry of a storage device or other type of processing device comprises a digital input detector and an adaptive power supply. The digital input detector comprises an input transistor. The adaptive power supply provides a variable supply voltage to the digital input detector that varies with a threshold voltage of the input transistor. In one embodiment, the variable supply voltage provided to the digital input detector by the adaptive power supply varies with the threshold…
DISK-BASED STORAGE DEVICE HAVING READ CHANNEL MEMORY THAT IS SELECTIVELY ACCESSIBLE TO DISK CONTROLLER
Granted: May 2, 2013
Application Number:
20130107391
A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises a disk controller and read channel circuitry, with the read channel circuitry…
Maskless Vortex Phase Shift Optical Direct Write Lithography
Granted: May 2, 2013
Application Number:
20130107240
The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.
DYNAMIC CLOCK DOMAIN BYPASS FOR SCAN CHAINS
Granted: April 25, 2013
Application Number:
20130103994
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than…
OPTICAL DISK PLAYBACK DEVICE WITH THREE-DIMENSIONAL PLAYBACK FUNCTIONALITY
Granted: April 25, 2013
Application Number:
20130100788
An optical disk playback device comprises one or more lasers, an optical assembly, an optical detector, and controller circuitry coupled to the optical detector. The optical assembly is configured to direct incident light from the one or more lasers so as to form first and second scanning spots on a surface of an optical disk, and is further configured to direct corresponding reflected light from the first and second scanning spots on the surface of the optical disk to the optical…
Systems and Methods for Out of Order Y-Sample Memory Management
Granted: April 18, 2013
Application Number:
20130097472
Systems and methods for out of order memory management.
Method and Apparatus for Power Management Control of an Embedded Memory Having Sleep and Shutdown Features
Granted: April 18, 2013
Application Number:
20130097445
A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii)…
METHODS AND SYSTEMS FOR AUTOMATED BACKUPS AND RECOVERY ON MULTI-OS PLATFORMS USING CONTROLLER BASED SNAPSHOTS
Granted: April 18, 2013
Application Number:
20130097397
A method for backing up and restoring data across multiple operating systems executed by a computing product executing computer implemented instructions, wherein each operating system includes a daemon. Embodiments may include receiving a backup initiation trigger from an initial, daemon on an initial operating system. This method may include relaying the backup initiation trigger to other daemons on other operating systems. This method may also include receiving snapshot requests from…
METHODS AND APPARATUS FOR IMPROVED RAID PARITY COMPUTATION IN A STORAGE CONTROLLER
Granted: April 18, 2013
Application Number:
20130097376
Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy…
ADDRESS LEARNING AND AGING FOR NETWORK BRIDGING IN A NETWORK PROCESSOR
Granted: April 18, 2013
Application Number:
20130097345
Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination…
Direct Memory Access With On-The-Fly Generation of Frame Information For Unrestricted Motion Vectors
Granted: April 18, 2013
Application Number:
20130094586
A method for performing motion estimation based on at least a first VOP stored in a memory includes the steps of: receiving a request to read a data block indicative of at least a portion of the first VOP for predicting a second VOP that is temporally adjacent to the first VOP; utilizing a DMA module for determining whether the data block is a UMV block; translating a block address for retrieving at least a portion of the data block from the memory as a function of one or more parameters…
APPARATUS AND METHODS FOR PERFORMING BLOCK MATCHING ON A VIDEO STREAM
Granted: April 18, 2013
Application Number:
20130094567
A data processing system for processing a video stream comprises memory array circuitry, memory access circuitry, and video processing circuitry. The memory array circuitry is characterized by a width and a height. The memory access circuitry is operative to cause, through a series of write operations, a series of two-dimensional data representations of different respective regions in a frame of the video stream to be stored in the memory array circuitry. The write operations occur such…
DYNAMIC VOLTAGE DROP AWARE CLOCK INSERTION TOOL
Granted: April 11, 2013
Application Number:
20130088275
A clock tree power decoupling system includes a pre-decoupling processor that provides a clock tree that supports a critical timing path condition. The clock tree power decoupling system also includes a clock tree power decoupler having a clock tree module that identifies clock buffers in the clock tree corresponding to synchronous start and end points of the critical timing path condition, and a power decoupling module that inserts a decoupling capacitance proximate the clock buffers in…
Thread Synchronization in a Multi-Thread, Multi-Flow Network Communications Processor Architecture
Granted: April 11, 2013
Application Number:
20130089109
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A…
Modifying Data Streams without Reordering in a Multi-Thread, Multi-Flow Network Communications Processor Architecture
Granted: April 11, 2013
Application Number:
20130089099
Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A scheduler generates contexts corresponding to tasks received by the packet classification processor from corresponding processing modules, each context corresponding to a given flow, and stores each context in a corresponding per-flow first-in, first-out buffer of the scheduler. A packet modifier generates a modified…
Changing a Flow Identifier of a Packet in a Multi-Thread, Multi-Flow Network Processor
Granted: April 11, 2013
Application Number:
20130089098
Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification processor determines, independent of a flow identifier of the received task, control data corresponding to each task. A multi-thread instruction engine processes threads of instructions corresponding to received tasks, each task corresponding to a packet flow of the network processor and…
