PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL
Granted: April 11, 2013
Application Number:
20130091403
The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder…
HARDWARE QUEUE FOR TRANSPARENT DEBUG
Granted: April 11, 2013
Application Number:
20130091388
A method for transparent debug of a hardware queue and recreation of an operational scenario comprising: use of a computer device to: monitor a plurality of inputs and outputs from a plurality of hardware queues associated as parts of a design; receive a request to save from an external source; pause one or more hardware queues upon command; receive hardware queue information from at least one of the paused hardware queues; dump said hardware queue information from at least one paused…
Early Cache Eviction in a Multi-Flow Network Processor Architecture
Granted: April 11, 2013
Application Number:
20130091330
Described embodiments provide an input/output interface of a network processor that generates a request to store received packets to a system cache. If an entry associated with the received packet does not exist in the system cache, the system cache determines whether a backpressure indicator of the system cache is set. If the backpressure indicator is set, the received packet is written to the shared memory. If the backpressure indicator is not set, the system cache determines whether…
SYSTEM AND METHOD OF AUTOMATED DESIGN AUGMENTATION FOR EFFICIENT HIERARCHICAL IMPLEMENTATION
Granted: April 4, 2013
Application Number:
20130086540
A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation…
SCALABLE STORAGE DEVICES
Granted: April 4, 2013
Application Number:
20130086336
Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process…
Task Queuing in a Multi-Flow Network Processor Architecture
Granted: April 4, 2013
Application Number:
20130086332
Described embodiments generate tasks corresponding to each packet received by a network processor. A destination processing module receives a task and determines, based on the task size, a queue in which to store the task, and whether the task is larger than space available within a current memory block of the queue. If the task is larger, an address of a next memory block in a memory is determined, and the address is provided to a source processing module of the task. The source…
STORAGE CACHING ACCELERATION THROUGH USAGE OF R5 PROTECTED FAST TIER
Granted: April 4, 2013
Application Number:
20130086300
A data storage system with redundant SSD cache includes an SSD cache organized into logical stripes, each logical stripe having several logical blocks. The logical blocks of each stripe are organized into logical data blocks and one logical parity block. Data may be written to the SSD cache by performing an exclusive disjunction operation on the logical parity block, the new data and the existing data in logical stripe to update the parity block, then writing the new data over the…
HARDWARE-BASED INTER-TRACK INTERFERENCE MITIGATION IN MAGNETIC RECORDING SYSTEMS WITH READ CHANNEL STORAGE OF CANCELATION DATA
Granted: April 4, 2013
Application Number:
20130083418
Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) cancellation data is stored in a memory of a read channel of a magnetic recording system. The memory can be in a write data path or a read data path of the read channel. The inter-track interference cancellation data is optionally provided to an inter-track interference mitigation circuit using at least a portion of a write data path, for…
TIMING SIGNOFF FOR MAXIMUM PROFIT
Granted: March 28, 2013
Application Number:
20130080198
A method of estimating a profit margin for an IC chip includes providing design, manufacturing and financial input data for the IC chip and determining a ratio of performing to manufactured IC chips using chip yields apart from timing. The method of estimating a profit margin also includes characterizing IC chip performance corresponding to clock timing and on-chip-variation (OCV) margins and calculating price and costs corresponding to design, manufacturing and testing of the IC chip.…
IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
Granted: March 28, 2013
Application Number:
20130080988
A method of manufacturing an electronic circuit employing a flexible ramptime limit and an electronic circuit are disclosed. In one embodiment, the method includes: (1) physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, (2) performing a timing test on the physically synthesized electronic circuit employing the flexible ramptime limits and a processor and (3) determining if there is a violation of the flexible ramptime limits.
TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLTAGE DROP INTO ACCOUNT
Granted: March 28, 2013
Application Number:
20130080986
A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.
METHODS AND APPARATUS FOR MARKING WRITES ON A WRITE-PROTECTED FAILED DEVICE TO AVOID READING STALE DATA IN A RAID STORAGE SYSTEM
Granted: March 28, 2013
Application Number:
20130080828
Methods and apparatus for improved building of a hot spare storage device in a RAID storage system while avoiding reading of stale data from a failed storage device. In the recovery mode of the failed device, all data is write protected on the failed device. A RAID storage controller may copy as much readable data as possible from the failed device to the hot spare storage device. Unreadable data may be rebuilt using redundant information of the logical volume. Write requests directed to…
STORAGE CACHING/TIERING ACCELERATION THROUGH STAGGERED ASYMMETRIC CACHING
Granted: March 28, 2013
Application Number:
20130080696
A multi-tiered system of data storage includes a plurality of data storage solutions. The data storage solutions are organized such that the each progressively faster, more expensive solution serves as a cache for the previous solution, and each solution includes a dedicated data block to store individual data sets, newly written in a plurality of write operations, for later migration to slower data storage solutions in a single write operation.
SYSTEM AND METHOD FOR OPTIMIZING THERMAL MANAGEMENT FOR A STORAGE CONTROLLER CACHE
Granted: March 28, 2013
Application Number:
20130080679
The present invention is directed to a method for optimizing thermal management for a storage controller cache of a data storage system. The method allows for pending writes of a storage controller to be selectively provided to solid-state device (SSD) module(s) of the controller in a manner which allows operating temperatures of the SSD module(s) to be maintained within a thermal envelope.
APPARATUS AND METHODS FOR PERFORMING SEQUENCE DETECTION
Granted: March 28, 2013
Application Number:
20130077717
An apparatus for performing sequence detection on a stream of incoming bits comprises a memory and circuitry coupled to the memory. The circuitry is operative, for each bit of the stream of incoming bits, to overwrite a first binary number presently stored in the memory with a second binary number, and to provide an output indicative of when the second binary number is equal to a predetermined value. The output indicative of when the second binary number is equal to the predetermined…
FRACTIONAL REDUNDANT ARRAY OF SILICON INDEPENDENT ELEMENTS
Granted: March 21, 2013
Application Number:
20130073895
Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such…
ENCLOSURE-INTEGRATED HANDLE FEATURES FOR MOUNTING STORAGE DEVICES
Granted: March 21, 2013
Application Number:
20130070422
Systems and methods are hereby provided for enclosures having integrated handle features for storing one or more storage devices. The system includes a rigid frame and multiple bays. Each bay includes a body movably attached to the frame, wherein repositioning of the body with respect to the frame is restricted by at least one holding element of the frame to a limited range of motion. The body defines a receptacle for receiving and holding a storage device. Each bay also includes a lever…
LEAD FRAME DESIGN TO IMPROVE RELIABILITY
Granted: March 21, 2013
Application Number:
20130067743
An electronic device package 100 comprising a lead frame 105 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.
Switching Clock Sources
Granted: March 14, 2013
Application Number:
20130063197
A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the…
METHODS AND STRUCTURE FOR IMPROVED I/O SHIPPING IN A CLUSTERED STORAGE SYSTEM
Granted: March 14, 2013
Application Number:
20130067123
Methods and structure for improved shipping of I/O requests among multiple storage controllers of a clustered storage system. Minimal processing of a received I/O request is performed in a first controller to determine whether the I/O request is directed to a logical volume that is owned by the first controller or to a logical volume owned by another controller. For requests to logical volumes owned by another controller, the original I/O request is modified to indicate the target device…
