METHODS AND STRUCTURE FOR IMPROVED PROCESSING OF I/O REQUESTS IN FAST PATH CIRCUITS OF A STORAGE CONTROLLER IN A CLUSTERED STORAGE SYSTEM
Granted: March 14, 2013
Application Number:
20130067125
Methods and structure for improved processing of fast path I/O requests in a clustered storage system. In a storage controller of a clustered storage system, the controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing stack (typically implemented as programmed instructions) for processing I/O…
METHODS AND STRUCTURE FOR TASK MANAGEMENT IN STORAGE CONTROLLERS OF A CLUSTERED STORAGE SYSTEM
Granted: March 14, 2013
Application Number:
20130067161
Methods and structure for task management in storage controllers of a clustered storage system. An initiator storage controller of the clustered storage system ships I/O requests for processing to a target storage controller of the system. Responsive to a need to abort a previously shipped I/O request, the initiator storage controller transmits a task management message to the target storage controller. The task management message identifies one or more previously shipped I/O requests to…
METHODS AND STRUCTURE FOR LOAD BALANCING OF BACKGROUND TASKS BETWEEN STORAGE CONTROLLERS IN A CLUSTERED STORAGE ENVIRONMENT
Granted: March 14, 2013
Application Number:
20130067162
Methods and structure for load balancing of background tasks between storage controllers are provided. An exemplary active storage controller comprises a front-end interface that receives host Input/Output (I/O) requests directed to a logical volume, a back-end interface that couples with one or more of storage devices provisioning the logical volume, and a control unit. The control unit processes the host I/O requests directed to the logical volume, identifies a background processing…
METHODS AND STRUCTURE FOR IMPROVED BUFFER ALLOCATION IN A STORAGE CONTROLLER
Granted: March 14, 2013
Application Number:
20130067172
Methods and structure for improved buffer management in a storage controller. A plurality of processes in the controller each transmits buffer management requests to buffer management control logic. A plurality of reserved portions and a remaining non-reserved portion are defined in a shared pool memory managed by the buffer management control logic. Each reserved portion is defined as a corresponding minimum amount of memory of the shared pool. Each reserved portion is associated with a…
CONTEXT-SPECIFIC STORAGE IN MULTI-PROCESSOR OR MULTI-THREADED ENVIRONMENTS USING TRANSLATION LOOK-ASIDE BUFFERS
Granted: March 14, 2013
Application Number:
20130067195
A method for maintaining context-specific symbols in a multi-core or multi-threaded processing environment may include, but is not limited to: partitioning a virtual address space into at least one portion associated with the storage of one or more context-specific symbols accessible by at least a first processing core and a second processing core; defining at least one context-specific symbol; storing the at least one context specific symbol to the at least one portion of the virtual…
METHODS AND STRUCTURE FOR RESUMING BACKGROUND TASKS IN A CLUSTERED STORAGE ENVIRONMENT
Granted: March 14, 2013
Application Number:
20130067274
Methods and structure for resuming background tasks in a storage environment. storage controller. The system is operable to receive host Input/Output (I/O) requests directed to a logical volume, and to couple with one or more of storage devices provisioning the logical volume. The system is further operable to process the host I/O requests directed to the logical volume, to initiate a background processing task distinct from the host I/O requests and related to the logical volume, and to…
METHODS AND STRUCTURE FOR MANAGING VISIBILITY OF DEVICES IN A CLUSTERED STORAGE SYSTEM
Granted: March 14, 2013
Application Number:
20130067569
Methods and system for implementing a clustered storage solution are provided. One embodiment is a storage controller that communicatively couples a host system with a storage device. The storage controller comprises an interface and a control unit. The interface is operable to communicate with the storage device. The control unit is operable to identify ownership information for a storage device, and to determine if the storage controller is authorized to access the storage device based…
POWER CONTROLLER FOR SOC POWER GATING APPLICATIONS
Granted: March 7, 2013
Application Number:
20130057338
A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current…
METHOD AND APPARATUS FOR CONSOLIDATING BOOT DRIVES AND IMPROVING RELIABILITY/AVAILABILITY/SERVICEABILITY IN HIGH DENSITY SERVER ENVIRONMENTS
Granted: March 7, 2013
Application Number:
20130061029
The present invention is directed to a boot appliance for a data storage system. The boot appliance is a self-contained, pre-configured device that serves as a boot device for multiple servers. The boot appliance contains multiple hard drives which are configured into one or more RAID volumes. Each volume is divided into multiple partitions, with each partition serving as the boot drive for any server connected to it. The boot appliance provides its own environmental controls and…
Multi-Level LDPC Layer Decoder
Granted: March 7, 2013
Application Number:
20130061107
Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor…
METHOD AND SYSTEM FOR SHARED HIGH SPEED CACHE IN SAS SWITCHES
Granted: February 28, 2013
Application Number:
20130054883
A data storage system includes at least one host device configured to initiate a data request, at least one target device configured to store data, and a serial attached SCSI (SAS) switch coupled between the at least one host device and the at least one target device. The SAS switch includes a cache memory and includes control programming configured to determine whether data of the data request is stored in the cache is at least one of data stored in the cache memory of the SAS switch or…
APPARATUS AND SYSTEMS HAVING STORAGE DEVICES IN A SIDE ACCESSIBLE DRIVE SLED
Granted: February 28, 2013
Application Number:
20130050955
Apparatus and systems for improved access to storage devices from the sides of sleds mounted in storage enclosures. Embodiments provide apparatus and systems for a sled in a storage enclosure that provides access to storage devices on either side of the sled when the sled is slid forward out of its enclosure. Multiple sleds may be enclosed within a single enclosure to permit access to a portion of the storage devices in the enclosure hence reducing the problems of instability of the rack…
HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL
Granted: February 28, 2013
Application Number:
20130049799
A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the…
Staged Scenario Generation
Granted: February 21, 2013
Application Number:
20130047129
A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint…
METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER
Granted: February 21, 2013
Application Number:
20130043602
A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the…
SYSTEM FOR DYNAMICALLY ADAPTIVE CACHING
Granted: February 14, 2013
Application Number:
20130042064
The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and…
Time Synchronization Using Packet-Layer and Physical-Layer Protocols
Granted: February 14, 2013
Application Number:
20130039359
In certain embodiments, a slave clock node in a wireless packet network achieves time synchronization with a master clock node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure.…
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
Granted: February 7, 2013
Application Number:
20130036393
A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the…
METHOD FOR IMPROVING PERFORMANCE IN RAID SYSTEMS
Granted: February 7, 2013
Application Number:
20130036340
A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.
METHOD TO ALLOW STORAGE CACHE ACCELERATION WHEN THE SLOW TIER IS ON INDEPENDENT CONTROLLER
Granted: February 7, 2013
Application Number:
20130036265
The present invention is directed to a method for providing storage acceleration in a data storage system. In the data storage system described herein, multiple independent controllers may be utilized, such that a first storage controller may be connected to a first storage tier (ex.—a fast tier) which includes a solid-state drive, while a second storage controller may be connected to a second storage tier (ex.—a slower tier) which includes a hard disk drive. The accelerator…
