SYSTEM AND METHOD OF SPEECH COMPRESSION USING AN INTER FRAME PARAMETER CORRELATION
Granted: November 8, 2012
Application Number:
20120284020
The disclosure provides a speech encoder, decoder, speech processor and methods of encoding and decoding speech. In one embodiment, the speech encoder includes: (1) a speech frame generator configured to form a speech frame from an input speech signal, the speech frame having a length of multiple samples, (2) a speech frame processor configured to determine if the speech frame is a subsequent voiced frame of a group of consecutive voiced frames and, based thereon, perform speech analysis…
INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS
Granted: November 8, 2012
Application Number:
20120284679
A computer-executed method for designing dummy metal object locations in an integrated circuit design. The method comprises the steps of: a) receiving an integrated circuit design as input; b) finding areas of the integrated circuit design that do not meet a minimum metal density requirement; c) finding areas of the integrated circuit design having a critical timing path; d) blocking empty routing tracks that are adjacent to critical nets of the critical timing paths located in step (c),…
MOBILE COMMUNICATION DEVICE APPARATUS HAVING MULTIPLE MOBILE DEVICES
Granted: November 8, 2012
Application Number:
20120282980
A mobile communication device having a plurality of mobile devices coupled to one another. The mobile communication device includes a first mobile device that has a screen display portion and a user input portion. The mobile communication device also includes at least one second mobile device detachably coupled to the first mobile device. The first mobile device is configured to function as a first standalone mobile communication device, and the second mobile device is configured to…
Cryptographic Random Number Generator Using Finite Field Operations
Granted: November 1, 2012
Application Number:
20120278372
An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations…
REMOTE EXECUTION OF RAID IN LARGE TOPOLOGIES
Granted: November 1, 2012
Application Number:
20120278552
A SAS expander for use in a SAS topology includes a receiving portion and a controller. The receiving portion is configured to receive a remote RAID instruction from a root host bus adapter. The controller is configured to execute the instruction to manage a RAID volume in accordance with a RAID management task specified by the instruction.
CENTRALIZED POWER AND HEAT MANAGEMENT FOR DATA DISK DRIVES OF A DATA STORAGE SYSTEM
Granted: November 1, 2012
Application Number:
20120278642
A method of controlling spinning of data disk drives, a data storage system including multiple data disk drives and a power zone aware device are disclosed herein. In one embodiment, the power zone aware device includes: (1) a policy module configured to define at least one power zone in the data storage system and assign a power zone policy thereto and (2) a management module coupled configured to direct operation of data disk drives in the power zone based on the power zone policy.
METHODS AND STRUCTURE FOR DEBUGGING DDR MEMORY OF A STORAGE CONTROLLER
Granted: November 1, 2012
Application Number:
20120278662
Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double…
Method and Apparatus for Generating Memory Models and Timing Database
Granted: November 1, 2012
Application Number:
20120278775
A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets…
SIGNAL DELAY SKEW REDUCTION SYSTEM
Granted: November 1, 2012
Application Number:
20120278783
A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path…
METHOD FOR COMPUTING IO REDISTRIBUTION ROUTING
Granted: October 25, 2012
Application Number:
20120272203
A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.
METHOD AND SYSTEM FOR DYNAMICALLY EXPANDABLE SOFTWARE BASED BAD BLOCK MANAGEMENT
Granted: October 18, 2012
Application Number:
20120262815
A method and system for tracking a sequence of bad blocks in a RAID system by storing the logical block address of the first bad block and the number of bad blocks in the sequence is disclosed. The method and system may also track multiple sequences of bad blocks by storing a memory pointer to the next sequence in each previous sequence in an expandable linked list configuration.
Double-Step CORDIC Processing for Conventional Signed Arithmetic With Decision Postponing
Granted: October 18, 2012
Application Number:
20120265796
A double-step CORDIC algorithm is implemented for conventional signed arithmetic using multiple iteration stages in which at least one stage implements decision postponing, in which the decision for each stage is delayed until the next stage. In one implementation, the decision for the previous stage is implemented in parallel with the execution of CORDIC equation functions for the current stage. Implementing the double-step CORDIC with decision postponing algorithm can increase the…
FULLY DIFFERENTIAL SIGNAL PEAK DETECTION ARCHITECTURE
Granted: September 27, 2012
Application Number:
20120242327
A signal detector includes a summation unit connected to offset first and second input signals representing a differential input signal into two offset pairs of first and second signals. The signal detector also includes a detection unit connected to select the first signal from one of the offset pairs of first and second signals and the second signal from the other of the offset pairs in an overlap portion of the first and second signals to form a complementary pair of overlap signals…
MOISTURE BARRIER FOR A WIRE BOND
Granted: September 6, 2012
Application Number:
20120223432
An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface
SOFT ATTENUATION OF HIGH-POWER SIGNALS
Granted: September 6, 2012
Application Number:
20120224684
In one embodiment, a high-level compensation (HLC) module receives samples of an input signal and determines whether a magnitude of each sample, represented in a linear domain, is relatively low or relatively high by comparing the magnitude to a threshold. If a sample is less than or equal to the threshold, then it is considered to have a relatively low magnitude and the sample is not attenuated. If a sample is greater than the threshold, then it is considered to have a relatively high…
MERGING A STORAGE CLUSTER INTO ANOTHER STORAGE CLUSTER
Granted: September 6, 2012
Application Number:
20120226669
A method for merging a source electronic memory storage cluster into a destination electronic memory storage cluster may include designating a source storage cluster having a first configuration; designating a destination storage cluster having a second configuration; receiving a configuration database including mapping information associated with the first configuration of the source storage cluster; merging the configuration database for the source storage cluster into the destination…
REDUNDANT ARRAY OF INEXPENSIVE DISKS (RAID) SYSTEM CONFIGURED TO REDUCE REBUILD TIME AND TO PREVENT DATA SPRAWL
Granted: September 6, 2012
Application Number:
20120226853
A RAID system is provided in which, in the event that a rebuild is to be performed for one of the PDs, a filter driver of the operating system of the computer of the RAID system informs the RAID controller of the RAID system of addresses in the virtual memory that are unused. Unused virtual memory addresses are those which have never been written by the OS as well as those which have been written by the OS and subsequently freed by the OS. The RAID controller translates the unused…
METHOD FOR DETECTING SHORT BURST ERRORS IN LDPC SYSTEM
Granted: September 6, 2012
Application Number:
20120226958
The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gat is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and…
UTILIZING TWO ALGORITHMS TO DETERMINE A DELAY VALUE FOR TRAINING DDR3 MEMORY
Granted: August 30, 2012
Application Number:
20120218841
A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe…
Mode Latching Buffer Circuit
Granted: August 23, 2012
Application Number:
20120212256
A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator…
