ITERATIVE-DIVISION OPERATIONS SUCH AS FOR HEADER COMPRESSION IN PACKET-BASED COMMUNICATIONS
Granted: August 23, 2012
Application Number:
20120215824
In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments…
BINARY-SHIFT OPERATIONS SUCH AS FOR HEADER COMPRESSION IN PACKET-BASED COMMUNICATIONS
Granted: August 23, 2012
Application Number:
20120215939
In one embodiment of a header-compression method, a timestamp value is divided by a stride value using a plurality of binary-shift operations corresponding to a Taylor expansion series of the reciprocal stride value in a base of ½. When the division-logic circuitry of an arithmetic logic unit in the corresponding communication device is not designed to handle operands that can accommodate the length of the timestamp and/or stride values, the header-compression method can advantageously…
DECOUPLING CAPACITOR
Granted: August 23, 2012
Application Number:
20120212878
An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and…
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion
Granted: August 16, 2012
Application Number:
20120210287
Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second…
CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE
Granted: August 9, 2012
Application Number:
20120200322
Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first…
TIME-DOMAIN ACOUSTIC ECHO CONTROL
Granted: August 9, 2012
Application Number:
20120201370
In one embodiment, an acoustic echo control (AEC) module receives an outgoing signal and an incoming signal, which, at various times, contains acoustic echo corresponding to the outgoing signal. The AEC module has a delay estimation block that estimates, in the time domain, the echo delay using an adaptive filtering technique. This delay estimation is used to align samples of the incoming signal having acoustic echo with the corresponding samples of the outgoing signal from which the…
IMPLEMENTING OPTIMAL STORAGE TIER CONFIGURATIONS FOR A WORKLOAD IN A DYNAMIC STORAGE TIERING SYSTEM
Granted: August 9, 2012
Application Number:
20120203999
A method for Dynamic Storage Tiering (DST) may include identifying a first storage tier with a performance characteristic. The method may include monitoring the utilization of the first storage tier to detect the placement of a hot spot. The method may include logically dividing a continuous range of a plurality of logical addresses into at least a first segment and a second segment so the first segment includes a proportionally larger amount of the hot spot. The method may include…
INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
Granted: August 2, 2012
Application Number:
20120194217
One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within…
METHODS AND SYSTEMS FOR TRACKING DATA ACTIVITY LEVELS
Granted: August 2, 2012
Application Number:
20120198105
methods and systems for monitoring data activity may include various operations, including, but not limited to: modifying a value of at least one counter in response to one or more input/output requests directed to at least one data storage region during a first time interval; storing a first cumulative value of the counter modified in response to one or more input/output requests directed to at least one data storage region during the first time interval following the expiration of the…
METHODS AND SYSTEMS FOR MIGRATING DATA BETWEEN STORAGE TIERS
Granted: August 2, 2012
Application Number:
20120198107
Methods and systems for migrating data between storage tiers may include various operations, including, but not limited to: determining at least one activity index of at least one data storage region; receiving an input/output request addressing at least one data segment included in the at least one data storage region; qualifying a data segment addressed by the input/output request for migration to at least one higher-performing storage device; and adding a data segment reference…
SERDES JITTER TOLERANCE BIST IN PRODUCTION LOOPBACK TESTING WITH ENHANCED SPREAD SPECTRUM CLOCK GENERATION CIRCUIT
Granted: July 26, 2012
Application Number:
20120189086
A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local…
METHODS AND SYSTEMS FOR IMPROVED STORAGE REPLICATION MANAGEMENT AND SERVICE CONTINUANCE IN A COMPUTING ENTERPRISE
Granted: July 26, 2012
Application Number:
20120192006
Systems and methods for management of replicated storage. Features and aspects hereof provide management of data replication among a plurality of storage systems in a manner substantially transparent to host systems attached to the storage systems. The storage systems are coupled to one another through a replication link. One storage systems is designated the primary storage system and all others are designated secondary storage systems. A common logical volume is defined with a common…
METHOD AND APPARATUS FOR DIVIDING A SINGLE SERIAL ENCLOSURE MANAGEMENT BIT STREAM INTO MULTIPLE ENCLOSURE MANAGEMENT BIT STREAMS AND FOR PROVIDING THE RESPECTIVE BIT STREAMS TO RESPECTIVE MIDPLANES
Granted: July 19, 2012
Application Number:
20120185626
A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane.
SYSTEMS CONFIGURED FOR IMPROVED STORAGE SYSTEM COMMUNICATION FOR N-WAY INTERCONNECTIVITY
Granted: July 19, 2012
Application Number:
20120185643
Storage systems configured for improved N-way connectivity among all of a plurality of storage controllers and all of a plurality of storage devices in the system. All controllers of the storage system are coupled through a switched fabric communication medium to all of the storage devices of the storage system. Thus, the back-end interface of each storage controller of the storage system is used for all communications with any of the storage devices as well as for any communications…
Basic Cell Architecture For Structured ASICs
Granted: July 12, 2012
Application Number:
20120175683
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be…
METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME
Granted: July 12, 2012
Application Number:
20120175702
An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of…
ROUND ROBIN ARBITER WITH MASK AND RESET MASK
Granted: July 5, 2012
Application Number:
20120173781
In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of…
SERIAL INPUT OUTPUT (SIO) PORT EXPANSION APPARATUS AND METHOD
Granted: July 5, 2012
Application Number:
20120173783
An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to…
METHOD AND SYSTEM FOR DATA DISTRIBUTION ACROSS AN ARRAY OF DRIVES
Granted: July 5, 2012
Application Number:
20120173812
Methods and systems for data distribution may include, but are not limited to: receiving a request from a client device to store data on a distributed storage system; obtaining a hierarchical cluster map representing the distributed storage system; selecting an object at a hierarchical level of the cluster map; determining if the hierarchical level is a drive level; and adding a drive identifier associated with the object to a drive identifier array if the hierarchical level is the drive…
Using Identification in Cache Memory for Parallel Requests
Granted: June 28, 2012
Application Number:
20120166694
In an exemplary computer system having one or more masters configured to the same slave memory using a protocol, such as the AMBA AXI protocol, a master provides an ID field to the memory as part of a data request, where the ID field has a line ID sub-field that represents a line ID value that uniquely identifies a particular cache line (or subset of cache lines) in the master, where the memory returns the line ID value back to the master along with the retrieved data. The master uses…
