HASH PROCESSING USING A PROCESSOR
Granted: June 28, 2012
Application Number:
20120166773
In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M(i), i=1, . . . , N, and the processing of each block M(i) includes t iterations of processing words of message schedule {Wt}. In each iteration possible, the DSP uses free operations to precalculate Wt and working variable values for use in…
METHOD AND SYSTEM FOR REDUCING POWER LOSS TO BACKUP IO START TIME OF A STORAGE DEVICE IN A STORAGE VIRTUALIZATION ENVIRONMENT
Granted: June 28, 2012
Application Number:
20120167079
A method and controller device for supplying battery power to a virtualized storage environment having a storage controller with a virtual machine manager and a second virtual machine. In response to a battery engaged event, the first virtual machine manager enables the image of the second virtual machine to be shared with a new instance of the second virtual machine so that the image does not have to be loaded therein. The first virtual machine manager then creates the new virtual…
SYSTEM AND METHOD FOR SYNCHRONOUS INTER-THREAD COMMUNICATION
Granted: June 28, 2012
Application Number:
20120167115
A method and apparatus configured to allow independent threads to communicate synchronously through a block of memory accessible to at least two independent threads for bi-directional communication. The method and apparatus simplify the conversion of computer code to a multi-threaded architecture by allowing threads to effectively interact through function calls and data returns.
CIRCUIT TO EFFICIENTLY HANDLE DATA MOVEMENT WITHIN A CACHE CONTROLLER OR ON-CHIP MEMORY PERIPHERAL
Granted: June 28, 2012
Application Number:
20120166730
The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.
INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
Granted: June 21, 2012
Application Number:
20120153430
A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a…
METHOD OF FABRICATION OF THROUGH-SUBSTRATE VIAS
Granted: June 21, 2012
Application Number:
20120153492
A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are…
MUSIC DETECTION BASED ON PAUSE ANALYSIS
Granted: June 21, 2012
Application Number:
20120155655
In one embodiment, a pause-based music detection (MD) module detects music by analyzing pauses in a received audio signal. The energy of each frame of the signal is compared to an energy threshold to determine whether the frame corresponds to background noise only (i.e., a pause) or sound such as speech or music. A window having a number of frames is analyzed to determine whether there is a pause within the window. If no pauses are detected in the window, then the current frame is…
MUSIC DETECTION USING SPECTRAL PEAK ANALYSIS
Granted: June 21, 2012
Application Number:
20120158401
In one embodiment, a music detection (MD) module accumulates sets of one or more frames and performs FFT processing on each set to recover a set of coefficients, each corresponding to a different frequency k. For each frame, the module identifies candidate musical tones by searching for peak values in the set of coefficients. If a coefficient corresponds to a peak, then a variable TONE[k] corresponding to the coefficient is set equal to one. Otherwise, the variable is set equal to zero.…
PERFORMANCE ENHANCED SYNCHRONIZATION MECHANISM WITH INTENSITY-ORIENTED READER API
Granted: June 21, 2012
Application Number:
20120158684
A method for synchronizing data operations in a multi-threaded computer system using a hybrid lock data structure that allows the computer system to dynamically implement a low contention cost lock or a low overhead cost lock based on the intensity of the memory operation.
Low Depth Circuit Design
Granted: June 21, 2012
Application Number:
20120159407
A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.
Method and Apparatus for Caching Prefetched Data
Granted: June 14, 2012
Application Number:
20120151149
A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache entries stored in the data cache comprises data that has been loaded using fetch ahead (FA); associating an identifier with each cache entry in the subset of cache entries, the identifier indicating whether the cache entry comprises data that has been loaded using FA; and implementing a cache…
Cache Line Fetching and Fetch Ahead Control Using Post Modification Information
Granted: June 14, 2012
Application Number:
20120151150
A method is provided for performing cache line fetching and/or cache fetch ahead in a processing system including at least one processor core and at least one data cache operatively coupled with the processor. The method includes the steps of: retrieving post modification information from the processor core and a memory address corresponding thereto; and the processing system performing, as a function of the post modification information and the memory address retrieved from the…
DATA PATH UTILIZATION FOR LOW LEVEL PATTERN GENERATION AND CHECKIING
Granted: June 7, 2012
Application Number:
20120140840
Decision modules are strategically located along with various modules to route signals from either a test pattern generator or the data link layer through the various modules for performing scrambling, encoding, and serializing procedures on the signals before transmission of the signals on a serial bus. Decision modules are strategically placed along with various modules to route signals to either a test pattern checker or the data link layer through the various modules for performing…
STATISTICAL INFORMATION COLLECTION FROM ONE OR MORE DEVICE(S) IN STORAGE COMMUNICATION WITH A COMPUTING PLATFORM
Granted: June 7, 2012
Application Number:
20120144069
A method includes addressing, through a command generated by an application executing on a computing platform, one or more device(s) in storage communication with the computing platform based on an appropriate communication link. The method also includes accessing, based on the addressing, a physical register of the one or more device(s) through an appropriate interface therein. Further, the method includes obtaining statistical information associated with a performance of the one or…
DATA PREFETCH IN SAS EXPANDERS
Granted: June 7, 2012
Application Number:
20120144082
A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the potential data blocks. The SAS expander stores the potential data blocks within a prefetch cache for future utilization within a data read.
METHODS AND STRUCTURE FOR STORAGE MIGRATION USING STORAGE ARRAY MANAGED SERVER AGENTS
Granted: June 7, 2012
Application Number:
20120144110
Methods and structure for improved migration of a logical volume storage migration using storage array managed server agents. Features and aspects hereof provide for a storage array (e.g., a RAID or other storage controller in a storage array) to manage the migration of a logical volume from a first physical storage volume to a second physical storage volume. The storage array cooperates with a server agent in each server configured to utilize the logical volume. The server agent…
METHOD AND DEVICE FOR UTILIZING APPLICATION-LEVEL PRIOR KNOWLEDGE FOR SELECTIVELY STORING DATA IN HIGHER PERFORMANCE MEDIA
Granted: June 7, 2012
Application Number:
20120144111
A method for selectively storing data identified by a software application in higher performance media may include executing control programming for an operating system and a software application hosted by the operating system. The software application assigns a first importance level to a first portion of data and a second importance level to a second portion of data. A first portion of data having the first importance level assigned by the software application is stored in a first…
VIRTUALIZED CLUSTER COMMUNICATION SYSTEM
Granted: June 7, 2012
Application Number:
20120144229
A method includes executing, in each of a number of nodes of a cluster communication system, a specialized instance of an operating system privileged to control a corresponding hypervisor configured to consolidate one or more VM(s) on a system hardware. The one or more VM(s) is configured to be associated with a non-privileged operating system. The method also includes providing a cluster stack associated with the specialized instance of the operating system on the each of the number of…
MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK
Granted: May 24, 2012
Application Number:
20120126364
An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank…
ENHANCED HEAT SPREADER FOR USE IN AN ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
Granted: May 24, 2012
Application Number:
20120126387
An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over the IC die along with a lateral portion extending from the concaved portion. The lateral portion has a surface area greater than a surface area of the concaved portion. A support member is further included that extends…
