Servo Channel With Equalizer Adaptation
Granted: June 25, 2015
Application Number:
20150179213
A servo system includes an equalizer circuit operable to filter digital servo data samples according to filter tap coefficients to yield equalized data, a detector circuit operable to apply a data detection algorithm to the equalized data to yield hard decisions, a convolution circuit operable to yield ideal digital data based on the hard decisions and on target values, a subtraction circuit operable to subtract the ideal digital data from the equalized data to yield an adaptation error…
ATTRIBUTE-BASED ASSISTANCE REQUEST SYSTEM FOR SEQUENTIALLY CONTACTING NEARBY CONTACTS WITHOUT HAVING THEM DIVULGE THEIR PRESENCE OR LOCATION
Granted: June 25, 2015
Application Number:
20150178312
An anonymous non-emergency help system matches capabilities of potential helpers to a requestor's needs. Helpers identify the type of assistance they are willing to provide and then agree to become available anonymously. The helpers are contacted sequentially for assistance based on proximity to the requestor. The nearest helper may choose to respond or decline the request. This anonymous location process occurs sequentially, awaiting a requestor-defined timeout, until one of the…
SYSTEM FOR EFFICIENT CACHING OF SWAP I/O AND/OR SIMILAR I/O PATTERN(S)
Granted: June 25, 2015
Application Number:
20150178201
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a write…
PREVENTING PROGRAMMING ERRORS FROM OCCURRING WHEN PROGRAMMING FLASH MEMORY CELLS
Granted: June 25, 2015
Application Number:
20150178152
Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash…
METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS
Granted: June 25, 2015
Application Number:
20150178149
An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the…
Systems and Methods for ATI Characterization
Granted: June 18, 2015
Application Number:
20150170706
Systems, methods, devices, circuits for data processing, and more particularly to data processing including adjacent track interference detection and/or characterization.
SKEW-AWARE DISK FORMAT FOR ARRAY READER BASED MAGNETIC RECORDING
Granted: June 18, 2015
Application Number:
20150170676
A method of reading data in a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head, selecting a mode for reading the data of a magnetic recording medium as a function of the position of the multi-reader head, and reading the data of the magnetic recording medium in the selected mode.
SYSTEM AND METHODS FOR CACHING A SMALL SIZE I/O TO IMPROVE CACHING DEVICE ENDURANCE
Granted: June 18, 2015
Application Number:
20150169458
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the cache-lines comprises a plurality of sub-cache lines. Each of the plurality of cache-lines and each of the plurality of sub-cache lines is associated with meta-data indicating one or more of a…
Illumination-Based Charging System for Portable Devices
Granted: June 11, 2015
Application Number:
20150162781
The disclosure is directed to illumination-based charging of one or more portable devices. According to an embodiment of the disclosure, an illumination-based charging pad includes a platform, a plurality of illumination sources, a plurality of photosensitive detectors, and a controller. The controller performs a scan by activating the illumination sources and detecting reflected illumination from an illuminated surface of at least one portable device disposed upon the platform. The…
LOW COMPLEXITY TONE/VOICE DISCRIMINATION METHOD USING A RISING EDGE OF A FREQUENCY POWER ENVELOPE
Granted: June 11, 2015
Application Number:
20150163363
An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received…
MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY
Granted: June 11, 2015
Application Number:
20150162057
An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is…
Slice Formatting and Interleaving for Interleaved Sectors
Granted: June 11, 2015
Application Number:
20150161045
A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within…
METHOD AND SYSTEM FOR PROGRAMMABLE SEQUENCER FOR PROCESSING I/O FOR VARIOUS PCIe DISK DRIVES
Granted: June 11, 2015
Application Number:
20150160886
Disclosed is a system and method for using a programmable sequencer to produce a required command for a particular standard, or format, being used by the PCIe disk drive. A PCIe disk drive may support a different standard, or format. A mix of any number of different standards, or formats, is permitted in the system and method. For each message, a different set of instructions can be selected for the conversion process.
Systems and Methods for Multi-Dimensional Data Processor Operational Marginalization
Granted: June 11, 2015
Application Number:
20150160869
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.
WIDE PORT EMULATION AT SERIAL ATTACHED SCSI EXPANDERS
Granted: June 4, 2015
Application Number:
20150154138
Methods and structure for emulating wide ports at an expander are provided. An exemplary system includes a Serial Attached Small Computer System Interface (SAS) expander. The expander includes a plurality of physical links, and a controller. The controller is able to identify a physical link coupled with a device, to generate a plurality of virtual physical links that are configured as a virtual wide port coupled with the device, and to present the virtual wide port at the expander in…
SYSTEM AND METHOD TO INTERLEAVE MEMORY
Granted: June 4, 2015
Application Number:
20150154114
A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a…
Integrated Frequency Multiplier and Slot Antenna
Granted: May 28, 2015
Application Number:
20150145740
A metal substrate with a slot therein forms a slot antenna, the slot having a major axis and a minor axis. A dielectric layer has a plurality of terminals disposed on or in the dielectric layer and the layer is attached on one surface of the substrate. The terminals of a non-linear device, such as a diode, are connected to corresponding terminals of the dielectric layer. The non-linear device is positioned proximate the slot and is substantially aligned with a minor axis of the slot. A…
Read Retry For Non-Volatile Memories
Granted: May 28, 2015
Application Number:
20150149840
An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based…
ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS
Granted: May 28, 2015
Application Number:
20150149698
Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the…
INCREMENTAL UPDATES FOR ORDERED MULTI-FIELD CLASSIFICATION RULES WHEN REPRESENTED BY A TREE OF LONGEST PREFIX MATCHING TABLES
Granted: May 28, 2015
Application Number:
20150149395
An apparatus includes a memory and a processor. The memory may be configured to store at least a portion of a multi-level tree representation of an ordered multi-field rule-based classification list. The tree representation includes at least one non-leaf level and one or more leaf levels. Each entry in the at least one non-leaf level contains a count value indicating a number of rules having a matching field. Entries in at least one of the one or more leaf levels include rule pointers…
