CONFIGURABLE STORAGE ARRAY CONTROLLER
Granted: October 7, 2010
Application Number:
20100257301
A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.
THREE-DIMENSIONAL ELECTRONICS PACKAGE
Granted: September 30, 2010
Application Number:
20100244276
An electronics package 100 comprising a substrate 105 having a planar surface 107, a memory die 110 and a logic die 120. Memory circuit components 112 interconnected to memory die contacts 114 located on an outer surface 116 of a face 118 of the memory die. Logic circuit components 122 interconnected to logic die contacts 124 located on an outer surface 126 of a face 128 of the logic die. Memory die contacts and the logic die contacts are interconnected such that the face of the memory…
SYSTEMS AND METHODS FOR INFORMATION SECURITY USING ONE-TIME PAD
Granted: September 30, 2010
Application Number:
20100246811
A method of verifying a password and methods of encryption and decryption using a key generated from a one-time pad. In one embodiment, the method of verifying includes: (1) receiving a password attempt, (2) retrieving a pointer from memory, (3) searching a one-time pad based on the pointer to retrieve a password, (4) comparing the password attempt with the password and (5) generating a new pointer if the password attempt matches the password.
SYSTEM FOR DATA SECURITY USING USER SELECTABLE ONE-TIME PAD
Granted: September 30, 2010
Application Number:
20100246817
A method of generating a key, a method of encrypting a message and an encryption/decryption system. In one embodiment, the method of generating the key includes: (1) selecting a common document to serve as a one-time pad, (2) generating a pointer, (3) searching the common document based on the pointer and (4) retrieving a key from the common document.
COMPUTER STORAGE APPARATUS FOR MULTI-TIERED DATA SECURITY
Granted: September 30, 2010
Application Number:
20100250602
A computer storage apparatus. In one embodiment, the apparatus includes: (1) primary file storage, (2) a controller coupled to said primary file storage and configured to provide an interface by which data is communicated therewith, (3) formula/offset file storage coupled to said controller and configured to store at least one formula/offset and (4) pointer file storage coupled to said controller and configured to store at least one pointer, said controller further configured to provide…
BUS ARBITRATION SYSTEM, A METHOD OF CONNECTING DEVICES OF AN IC EMPLOYING A BUS SYSTEM AND AN IC
Granted: September 30, 2010
Application Number:
20100250808
A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to…
DEVICE FOR DATA SECURITY USING USER SELECTABLE ONE-TIME PAD
Granted: September 30, 2010
Application Number:
20100250968
Devices for securing data and method of managing a one-time pad stored in nonvolatile memory of a device. In one embodiment, the device for securing data includes: (1) a nonvolatile memory, (2) a nonvolatile memory controller coupled to the nonvolatile memory and configured to cooperate with the nonvolatile memory to make a key available when a password provided to the device is valid and (3) a self-destruct circuit coupled to the nonvolatile memory and configured to corrupt at least…
Data Volume Rebuilder and Methods for Arranging Data Volumes for Improved RAID Reconstruction Performance
Granted: September 30, 2010
Application Number:
20100251012
A data volume rebuilder reduces the time required to reconstruct lost data in a RAID protected data volume operating with a failed physical disk drive. A data volume rebuilder uses the remaining functioning physical disk drives in the RAID protected data volume operating with the failed disk to regenerate the lost data and populate a virtual hot spare store allocated in a separate RAID protected data volume. The recovered data is distributed across the physical disk drives supporting the…
HIGH SPEED PACKET FIFO OUTPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP
Granted: September 23, 2010
Application Number:
20100238938
Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is…
ALLEVIATING BLOCKING CASES IN A SAS SWITCH
Granted: September 23, 2010
Application Number:
20100241779
A first SAS expander including at least two phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.
HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP AND RETRANSMIT
Granted: September 23, 2010
Application Number:
20100238937
Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers.…
N+1 Protection Using a Processor-Based Protection Device
Granted: September 23, 2010
Application Number:
20100238794
In an N+1 protection scheme for a router in a data or telecommunications network, a processor-based protection unit has a replica device handle, corresponding to each of the N working units, stored in the protection unit's local memory. Each replica device handle is an image of the connections provided by the corresponding working unit. In one implementation, upon detection of a failure of one of the working units, the router's controller unit sends a single command to instruct the…
DC OFFSET DETECTION AND CORRECTION FOR USER TRAFFIC
Granted: September 2, 2010
Application Number:
20100219996
In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic…
APPARATUS AND METHODS FOR IMPROVED DUAL DEVICE LOOKUP IN A ZONING SAS EXPANDER
Granted: August 26, 2010
Application Number:
20100215041
Apparatus and methods for full address resolution in a zoning SAS expander. A single memory circuit is used in a zoning SAS expander to store zone information associated with the SAS address (e.g., WWN) of devices exchanging information through the expander. The source and destination addresses in a received SAS frame are used as inputs to the memory circuit to generate outputs of the memory circuit representing the source and destination zone group identifiers. These outputs are then…
PREDICTING A CONDITIONAL BIT VALUE FOR CONTINUING EXECUTION OF AN INSTRUCTION
Granted: August 26, 2010
Application Number:
20100217962
Methods and microprocessors are provided for continuing execution of an instruction, even though execution of the instruction depends on a value of a conditional bit (e.g., a flag bit or a predicated bit) that has not been determined. Rather than stalling execution of the instruction, a predicted value of the conditional bit is predicted and execution of the instruction is continued based on the predicted value of the conditional bit. If the predicted value matches a determined value of…
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
Granted: August 12, 2010
Application Number:
20100200993
Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and…
DEVICE AND METHOD FOR IMPROVED BATTERY CONDITION LEARN CYCLE
Granted: August 5, 2010
Application Number:
20100194341
Embodiments of the invention include a device and method for improved battery learn cycles for battery backup units within data storage devices. The backup unit includes a first battery pack, a corresponding charge capacity gauge, one or more second battery packs, a corresponding charge capacity gauge, and a controller switch configured to select only one battery pack for a learn cycle at any given time. The charge capacity gauges are such that, at the end of the learn cycle discharge…
DATA COMPRESSION METHOD AND APPARATUS
Granted: August 5, 2010
Application Number:
20100194607
Embodiments of the invention include a dictionary based data compression method, apparatus and system that is not based on either the LZ77 compression algorithm or the LZ78 compression algorithm, but includes many features of the LZW compression algorithm. The data compression method includes creating a mapping table of the messages in the alphabet of messages to a corresponding plurality of codewords, maintaining a dictionary including a mapping table of a first codeword and a second…
Controller, Program and Methods for Communicating With Devices Coupled to the Controller
Granted: July 29, 2010
Application Number:
20100191871
A controller coupled to a redundant array of inexpensive disks (RAID) includes a processor and a non-volatile memory element. The processor has an input/output port that is configurable in one of an open-drain driver configuration, a high-impedance driver configuration and a totem-pole driver configuration. The totem-pole driver configuration is capable of supplying sufficient current to operate a slave device coupled to the input/output port. Firmware stored in the non-volatile memory…
RAID Converter and Methods for Transforming a First RAID Array to a Second RAID Array Without Creating a Backup Copy
Granted: July 29, 2010
Application Number:
20100191907
A system transforms data structures absent the need for a backup copy. The system transforms a first logical store in an initial logical arrangement to a desired logical arrangement where the data structures of the logical arrangements are different. The system uses a select sequence of data operations that moves data from its origin in the initial logical arrangement to a target location in the desired logical arrangement. The system generates and properly locates parity information…
