ERROR CORRECTION CAPABILITY ADJUSTMENT OF LDPC CODES FOR STORAGE DEVICE TESTING
Granted: July 22, 2010
Application Number:
20100185906
Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit…
AC/DC POWER SUPPLY, A METHOD OF DELIVERING DC POWER AT MULTIPLE VOLTAGES AND A COMPUTER DATA STORAGE SYSTEM EMPLOYING THE POWER SUPPLY OR THE METHOD
Granted: July 1, 2010
Application Number:
20100164280
An AC/DC power supply, a method of delivering DC power at multiple voltages and a computer data storage system. In one embodiment the AC/DC power supply includes: (1) a transformer having a primary winding couplable to an AC power source and a secondary winding inductively couplable to the primary winding and (2) multiple DC voltage rails coupled to the secondary winding at designated locations and configured to deliver power to loads coupled thereto, each of the DC voltage rails…
DATA STORAGE METHOD, APPARATUS AND SYSTEM FOR INTERRUPTED WRITE RECOVERY
Granted: July 1, 2010
Application Number:
20100169572
Embodiments of the invention include a method, apparatus and system for storing data that involves storing boundary information for data that is being written to a plurality of data storage devices. The method includes storing boundary information for a write operation of data to a plurality of data storage device, writing the data to the plurality of data storage devices and removing the recorded boundary information upon completion of the write operation of the data to the plurality of…
ANALYZER AND METHODS FOR ARCHITECTURALLY INDEPENDENT NOISE SENSITIVITY ANALYSIS OF INTEGRATED CIRCUITS HAVING A MEMORY STORAGE DEVICE
Granted: July 1, 2010
Application Number:
20100169850
Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes: (1) a circuit reservoir configured to receive and store a model of a circuit having at least one memory storage device to be analyzed, (2) a circuit parser configured to identify nodes of the model and (3) a circuit evaluator configured to apply a large test current to each of the nodes for…
LATCH AND DFF DESIGN WITH IMPROVED SOFT ERROR RATE AND A METHOD OF OPERATING A DFF
Granted: June 24, 2010
Application Number:
20100156494
A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair…
Method and System for Tuning Precision Continuous-Time Filters
Granted: June 24, 2010
Application Number:
20100156525
Described embodiments provide a method for calibrating a continuous-time filter having at least one adjustable parameter. A square-wave signal is filtered by a continuous-time filter having a cutoff frequency less than fs. The filtered signal is quantized at the rate fs. An N-point Fourier transform is performed of the quantized signal into N real output values and N imaginary output values. At least one of the real output values are accumulated to form a real output signal and at least…
Apparatus for Calculating an N-Point Discrete Fourier Transform
Granted: June 24, 2010
Application Number:
20100161700
Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least…
SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION
Granted: June 24, 2010
Application Number:
20100162058
Disclosed herein is a sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes: (1) an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and (2) a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan…
DFT TECHNIQUE TO APPLY A VARIABLE SCAN CLOCK INCLUDING A SCAN CLOCK MODIFIER ON AN IC
Granted: June 24, 2010
Application Number:
20100162060
A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic…
MODULATED CLOCK, AN IC INCLUDING THE MODULATED CLOCK AND A METHOD OF PROVIDING A MODULATED CLOCK SIGNAL FOR POWER CONTROL
Granted: June 17, 2010
Application Number:
20100150271
A modulated clock, a method of providing a modulated clock signal, an integrated circuit including a modulated clock and a library of cells including a modulated clock. In one embodiment, the modulated clock includes (1) a clock controller configured to generate a digital control stream and (2) clock logic circuitry having a first input configured to receive a clock signal and a second input configured to receive the digital control stream. The clock logic circuitry is configured to…
SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME
Granted: June 17, 2010
Application Number:
20100153897
A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional replacements of cells in at least one path in a circuit design with lower…
REAL-TIME CRITICAL PATH MARGIN VIOLATION DETECTOR, A METHOD OF MONITORING A PATH AND AN IC INCORPORATING THE DETECTOR OR METHOD
Granted: June 17, 2010
Application Number:
20100153896
A margin violation detector for detecting margin violations of critical paths, a method of monitoring data paths and an IC. In one embodiment, the margin violation detector includes: (1) a monitor flip-flop having a monitor input couplable to a critical path input of a capture flip-flop of a critical path, (2) an exclusive OR gate having a first input couplable to an output of the capture flip-flop and a second input couplable to an output of the monitor flip-flop and (3) a violation…
TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND SETUP VIOLATIONS OF AN INTEGRATED CIRCUIT AND A METHOD OF TIMING TESTING
Granted: June 17, 2010
Application Number:
20100153895
A timing error sampling generator, a path monitor, an IC, a method of performing timing tests and a library of cells. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored…
SOFT-ERROR DETECTION FOR ELECTRONIC-CIRCUIT REGISTERS
Granted: June 17, 2010
Application Number:
20100153824
In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then…
METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS
Granted: June 17, 2010
Application Number:
20100153795
A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay…
SCALING OF SMALL COMPUTER SYSTEM INTERFACE INPUT OUTPUT (SCSI I/O) REFERRALS
Granted: June 17, 2010
Application Number:
20100153613
A command is issued to a first data storage system for addressing a set of data and at least one of a first referral response including a referral to at least a second data storage system or at least a first subset of the set of data and the first referral response including the referral to the at least the second data storage system. The at least one of a first referral response including a referral to at least a second data storage system or at least a first subset of the set of data…
TRANSPORT AGNOSTIC SCSI I/O REFERRALS
Granted: June 17, 2010
Application Number:
20100153612
The present invention is a method for providing multi-pathing via Small Computer System Interface Input/Output (SCSI I/O) referral between an initiator and a storage cluster which are communicatively coupled via a network, the storage cluster including at least a first target device and a second target device. The method includes receiving an input/output (I/O) at the first target device from the initiator via the network. The I/O includes a data request. The method further includes…
METHOD OF GENERATING A RESTRICTED INLINE RESISTIVE FAULT PATTERN AND A TEST PATTERN GENERATOR
Granted: June 17, 2010
Application Number:
20100153056
A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.
Continuous Time - Decision Feedback Equalizer
Granted: June 17, 2010
Application Number:
20100150221
An apparatus comprises a summer suitable for subtracting a jfiltered feedback signal from an input; a symbol decision device suitable for receiving an output from the summer; a feedback filter suitable for filtering an output from the symbol decision device and for sending the filtered feedback signal to the summer, the feedback filter comprising an adjustable swing amplifier and an adjustable pole filter; and an adaptation algorithm suitable for simultaneously adapting both a pole…
Interleaver and de-interleaver for iterative code systems
Granted: June 10, 2010
Application Number:
20100146229
In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing…
