3-PRONG SECURITY/RELIABILITY/REAL-TIME DISTRIBUTED ARCHITECTURE OF INFORMATION HANDLING SYSTEM
Granted: June 3, 2010
Application Number:
20100138923
The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried nucleus is in operation, and a trusted authority for generating a secure protocol. The secure protocol controls the operation of the buried nucleus.
CPU INSTRUCTION RAM PARITY ERROR PROCEDURE
Granted: May 13, 2010
Application Number:
20100122150
A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives…
METHOD, APPARATUS AND SYSTEM FOR SERIAL ATTACHED SCSI (SAS) ZONING MANAGEMENT OF A DOMAIN USING END DEVICE GROUPING
Granted: May 6, 2010
Application Number:
20100115073
Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using end device grouping. A SAS end device grouping management application is configured to group SAS end devices, such as SAS initiator devices and SAS target devices, into any number of zones or zone configurations. The end device grouping application uses these defined zones to create a minimal number of zone groups, e.g., by creating one zone group per defined zone and populating the zone…
METHOD, APPARATUS AND SYSTEM FOR SERIAL ATTACHED SCSI (SAS) ZONING MANAGEMENT OF A DOMAIN USING CONNECTOR GROUPING
Granted: May 6, 2010
Application Number:
20100115163
Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using connector grouping. A connector grouping management application is configured to allow connectors on the edge of the ZPSDS to be grouped into defined zones. The defined zones are used to create a minimal number of zone groups and to configure the respective permissions of the zone groups. The connector grouping application then compares all existing zone groups for phys common to more than…
DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD
Granted: April 22, 2010
Application Number:
20100100859
A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be…
CHANNEL LENGTH SCALING FOR FOOTPRINT COMPATIBLE DIGITAL LIBRARY CELL DESIGN
Granted: April 15, 2010
Application Number:
20100095252
Effective GDS-based channel length scaling. A library cell is designed, and then the width of the polys is increased, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The method can be used in association with a 45 nm digital library cell. Specifically, a library cell having 40 nm polys is designed, and then the width of each of the polys is increased by 5 nm to 45 nm, and the polys and contacts are shifted in order to maintain…
CONTROL SIGNAL SOURCE REPLICATION
Granted: April 1, 2010
Application Number:
20100083195
Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one…
SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMADATE HIGH SPEED CIRCUITRY GROUND ISOLATION
Granted: March 18, 2010
Application Number:
20100067207
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
METHOD, APPARATUS AND SYSTEM FOR SERIAL ATTACHED SCSI (SAS) ZONING MANAGEMENT OF A DOMAIN USING INITIATOR ISOLATION
Granted: March 18, 2010
Application Number:
20100070662
Embodiments of the invention include a method and apparatus for managing SAS zoning using initiator isolation. The method includes assigning initiator devices in the SAS domain to a first initiator zone group, assigning target devices in the SAS domain to a second target zone group, and establishing an access control policy in which each of the initiator devices assigned to the first initiator zone group can communicate with each of the target devices assigned to the second target zone…
METHOD AND SYSTEM FOR RESOLVING CONFIGURATION CONFLICTS IN RAID SYSTEMS
Granted: March 18, 2010
Application Number:
20100070705
A software-based RAID system is provided that enables configuration conflicts to be detected and resolved between a PD that is logically present but physically missing, and a PD that is physically and logically present. In accordance with the invention, a determination is made as to whether such a configuration conflict exists, and if so, the logically-present, but physically missing, reference identifier associated with the PD is remapped to a port number that currently is not in use.
Package with Power and Ground Through Via
Granted: March 11, 2010
Application Number:
20100059865
A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such…
SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME
Granted: February 25, 2010
Application Number:
20100050144
A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to make first conditional replacements of cells in at least one path in a circuit design with lower leakage cells and estimate a delay and a slack of the at least one path based on the first conditional replacement and (2) a speed recovery module…
DETERMINING INDEX VALUES FOR BITS OF A BINARY VECTOR
Granted: February 18, 2010
Application Number:
20100042806
In one embodiment, the present invention determines index values corresponding to bits of a binary vector that have a value of 1. During each clock cycle, a masking technique is applied to M sub-vector index values, where each sub-vector index value corresponds to a different bit of a sub-vector of the binary vector. The masking technique is applied such that (i) the sub-vector index values that correspond to bits having a value of 0 are zeroed out and (ii) the sub-vector index values…
ERROR-FLOOR MITIGATION OF LDPC CODES USING TARGETED BIT ADJUSTMENTS
Granted: February 18, 2010
Application Number:
20100042890
Embodiments of the present invention are methods for breaking one or more trapping sets in a near codeword of a failed graph-based decoder, e.g., an LDPC decoder. The methods determine, from among all bit nodes associated with one or more unsatisfied check nodes in the near codeword, which bit nodes, i.e., the suspicious bit nodes or SBNs, are most likely to be erroneous bit nodes. The methods then perform a trial in which the values of one or more SBNs are altered and decoding is…
ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING
Granted: February 18, 2010
Application Number:
20100042891
In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder…
RECONFIGURABLE TWO'S-COMPLEMENT AND SIGN-MAGNITUDE CONVERTER
Granted: February 18, 2010
Application Number:
20100042892
In one embodiment, a reconfigurable two's-complement-to-sign-magnitude (2TSM) converter has two five-bit non-reconfigurable 2TSM converters and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second five-bit messages, respectively, from two's-complement-to-sign-magnitude format. In the ten-bit mode, the first and second non-reconfigurable 2TSM converters…
RECONFIGURABLE CYCLIC SHIFTER
Granted: February 18, 2010
Application Number:
20100042893
In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and…
ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING LMAXB-BASED SELECTION OF ALTERNATIVE LAYERED-DECODING SCHEDULES
Granted: February 18, 2010
Application Number:
20100042894
A decoder-implemented method for layered decoding that, when the decoder converges on a near codeword using an initial schedule, (i) selects a subsequent schedule from a schedule set based on the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes and (ii) re-performs decoding using the subsequent schedule. When used in an offline schedule-testing system, the layered-decoding method (i) identifies which schedules, out of a population of…
SELECTING LAYERED-DECODING SCHEDULES FOR OFFLINE TESTING
Granted: February 18, 2010
Application Number:
20100042895
A method for selecting a population of schedules of an n-layer decoder for offline schedule testing. The method identifies one or more triads, where a triad is a sequence of three layers where no layer is repeated. The method selects a set of schedules where each of the identified triads is contained in at least one schedule. The method associates each selected schedule with one or more key-layer values, where a key layer is the middle layer of a triad contained within the schedule.
ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING NON-STANDARD LAYERED-DECODING SCHEDULES
Granted: February 18, 2010
Application Number:
20100042896
A layered decoder that uses a non-standard schedule, where a non-standard schedule is a schedule where the frequency of one or more layers in the schedule is greater than one. When the layered decoder converges on a near codeword using an initial schedule, the layered decoder identifies the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes, and selects a subsequent non-standard schedule from a schedule set. The non-standard schedules in…
