METHOD AND SYSTEM FOR MODIFYING FIRMWARE IMAGE SETTINGS WITHIN DATA STORGAE DEVICE CONTROLLERS
Granted: February 18, 2010
Application Number:
20100042984
Embodiments of the invention include a method for modifying firmware settings within a data storage controller, such as a data storage controller used in a Redundant Array of Inexpensive Disks (RAID) storage array. The method includes extracting a sub-module from a firmware image stored in the controller, stripping off the sub-module's header, decompressing the remaining compressed image by replacing the stripped sub-module header and an extended image header in the compressed image with…
ADJUSTING INPUT SAMPLES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS
Granted: February 18, 2010
Application Number:
20100042905
In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations…
BREAKING UNKNOWN TRAPPING SETS USING A DATABASE OF KNOWN TRAPPING SETS
Granted: February 18, 2010
Application Number:
20100042904
In one embodiment, an LDPC decoder attempts to recover an originally-encoded LDPC codeword based on a set of channel soft-output values. If the decoder observes a trapping set, then the decoder compares the observed trapping set to known trapping sets stored in a trapping-set database to determine whether or not the observed trapping set is a known trapping set. If the observed trapping set is not known, then the decoder selects a most-dominant trapping set from the trapping-set database…
SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS
Granted: February 18, 2010
Application Number:
20100042897
In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages…
RECONFIGURABLE MINIMUM OPERATOR
Granted: February 18, 2010
Application Number:
20100042898
In one embodiment, a reconfigurable minimum operator has two five-bit non-reconfigurable minimum operators and is selectively configurable to operate in a five- or ten-bit mode. In five-bit mode, the first non-reconfigurable minimum operator determines whether a first five-bit message is less than a second five-bit message, and the second non-reconfigurable minimum operator determines whether a third five-bit message is less than a fourth five-bit message. In ten-bit mode, the first…
ERROR-FLOOR MITIGATION OF ERROR-CORRECTION CODES BY CHANGING THE DECODER ALPHABET
Granted: February 18, 2010
Application Number:
20100042902
In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be…
RECONFIGURABLE ADDER
Granted: February 18, 2010
Application Number:
20100042903
In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a…
BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME
Granted: February 4, 2010
Application Number:
20100031222
A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and…
Variable Node Processing Unit
Granted: February 4, 2010
Application Number:
20100030835
A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.
Method and Apparatus for Generating Memory Models and Timing Database
Granted: January 28, 2010
Application Number:
20100023904
A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource…
Method and Apparatus for Debugging Protocol Traffic Between Devices in Integrated Subsystems
Granted: January 28, 2010
Application Number:
20100023591
A method, apparatus, and computer instructions for a storage subsystem. This subsystem includes controller devices, storage devices, and a communications network. The communications network connects the controller devices and the storage devices. The communications network also includes a set of diagnostic outputs. The set of diagnostic outputs is configured to output data sent between two devices from the controller devices and the storage devices for monitoring.
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS
Granted: January 28, 2010
Application Number:
20100022060
The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain…
METHOD AND SYSTEM FOR PERFORMING RAID LEVEL MIGRATION
Granted: January 14, 2010
Application Number:
20100011162
A RAID level migration system and method are provided that enable RAID level migration to be performed without the use of a hardware RAID controller with NVRAM for storing the migration parameters. Eliminating the need for a hardware controller having NVRAM significantly reduces the costs associated with performing RAID level migration. The system and method are capable of migrating from any arbitrary RAID level to any other arbitrary RAID level.
Conveying Information With a PCI Express Tag Field
Granted: January 14, 2010
Application Number:
20100011146
A method for determining when all data has been sent for a given PCI Express bus command issued by a backend entity of a PCI Express bus device, by setting a PCI Express bus packet header tag field of a PCI Express bus packet to indicate a backend entity that originated the PCI Express bus command and whether the PCI Express bus packet is a last packet of the PCI Express bus command, and then inspecting the PCI Express bus packet header tag field of the PCI Express bus packet to…
TESTABLE TRISTATE BUS KEEPER
Granted: January 14, 2010
Application Number:
20100007371
A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the…
Devices and Methods for Matching Link Speeds Between Controllers and Controlled Devices
Granted: January 7, 2010
Application Number:
20100002599
A controller system for detecting and matching link speeds. The present invention provides for a controller system. The controller system is a first controller and a first port. The first port is located in the first controller and has a first link speed. The first controller is adapted to match the first link speed to a second link speed of a second port of a first controlled device that is connectable to the first controller.
Latch-based Random Access Memory
Granted: January 7, 2010
Application Number:
20100002526
A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.
Drive Box
Granted: January 7, 2010
Application Number:
20100002368
A rack mount drive blade system having a chassis and a drive blade. The chassis has at least one blade bay to accept a drive blade, where the chassis accepts the drive blade into the blade bay with the drive blade in a horizontal orientation. Each blade bay has chassis to blade electrical contacts including at least one cable having a length, for making electrical connections between the chassis and the drive blade. Each blade bay also has slot portions for engaging the drive blade along…
OPTIMIZED CACHE COHERENCY IN A DUAL-CONTROLLER STORAGE ARRAY
Granted: December 31, 2009
Application Number:
20090327600
Data is cached in a dual-controller storage array having a first cache controlled by a first controller, a second cache controlled by a second controller, and a shared array of persistent storage devices, such as disk drives. When one of the controllers receives a write request, it stores the data in persistent storage, stores a copy of that data in the first cache, and transmits identification data to the second controller that identifies the data written to persistent storage. Using…
METHOD, APPARATUS AND SYSTEM FOR SERIAL ATTACHED SCSI (SAS) DOMAIN MANAGEMENT
Granted: December 24, 2009
Application Number:
20090319652
Embodiments of the invention include a method, apparatus and system for providing a Serial Attached SCSI (SAS) domain management application using a domain overlay architecture. The method includes comparing user constructs or data sets defining an existing domain overlay with device data that identifies various network devices in at least one SAS domain, and binding the existing domain overlay to an SAS domain if the existing domain overlay and the SAS domain are uniquely associated…