METHOD FOR ESTIMATION OF TRACE INFORMATION BANDWIDTH REQUIREMENTS
Granted: December 24, 2009
Application Number:
20090319963
A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
Granted: December 3, 2009
Application Number:
20090294856
A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well…
FAST TURN ON ACTIVE DCAP CELL
Granted: December 3, 2009
Application Number:
20090295470
A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains…
Ranking and Prioritizing Point in Time Snapshots
Granted: December 3, 2009
Application Number:
20090300303
A storage area network system having a data storage means for storing computer data, a storage manager routine running on a client, the storage manager routine having functional elements for directing snapshots to be taken of the computer data on the data storage means, and a snapshot ranking manager for determining characteristics of the snapshots, and for selectively deleting given ones of the snapshots based at least in part on the characteristics of the snapshots. The characteristics…
Whisker-free lead frames
Granted: November 26, 2009
Application Number:
20090291321
A method of fabricating an interconnection between a region of copper material and a conducting region is disclosed. The method includes a step of forming a region of tin material and a step of forming a region of nickel material. The method also includes a step of melting the tin material to induce formation of a nickel/tin/copper intermetallic composition at an interface between the region of copper material and the conducting region. The region of tin material and the region of nickel…
Area Efficient First-In First-Out circuit
Granted: November 19, 2009
Application Number:
20090285045
A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the X memories has a size of N/X by M. Control logic receives the data from the write port, writes the data into at least one of the X memories in a serial write manner, reads the data from at least one of the X memories in a serial read manner,…
Integrated Circuit System Monitor
Granted: November 19, 2009
Application Number:
20090285261
A temperature monitoring circuit for an integrated circuit on a monolithic chip, the temperature monitoring circuit comprising a temperature sensor disposed on the monolithic chip, a system monitor disposed on the monolithic chip, and electrically conductive traces for electrically connecting the temperature sensor to the system monitor. In this manner, the temperature on the monolithic chip can be monitored by the integrated circuit itself, and appropriate action can be programmed to…
Computational Architecture for Soft Decoding
Granted: November 19, 2009
Application Number:
20090287980
A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel.…
ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLACEMENT OF PROCESS MONITORS IN AN INTEGRATED CIRCUIT
Granted: November 12, 2009
Application Number:
20090282381
An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical…
Decision Tree Representation of a Function
Granted: November 12, 2009
Application Number:
20090281969
An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other…
CRITICAL PATH MONITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
Granted: November 12, 2009
Application Number:
20090278576
A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the…
METHOD FOR ABATING EFFLUENT FROM AN ETCHING PROCESS
Granted: November 5, 2009
Application Number:
20090275204
A method for abating effluent from an etching process in one embodiment includes advancing etch gas product into a passageway of a gas connector in direct fluid communication with a first chamber of an interior void of an apparatus, advancing a gas from a gas source into said passageway of said gas connector at the same time said etch gas product is being advanced into said passageway, and advancing humidified gas from a humidified gas source into a second chamber of said interior void.
Unified Layer Stack Architecture
Granted: October 29, 2009
Application Number:
20090271755
A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest…
On Chip Local MOSFET Sizing
Granted: October 22, 2009
Application Number:
20090265675
A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space…
Storage Blade
Granted: October 15, 2009
Application Number:
20090257185
A blade-system computer component with a chassis and a blade. The chassis has a housing for a blade, chassis electrical contacts for making electrical connections to the blade, and two rails for engaging the blade along two sides of a length of the blade. Each of the two rails has a slider portion and a rack portion that both engage the blade, and are both disposed along an entire length of the two rails. The blade has blade electrical contacts for making electrical connections to the…
Heat Dissipation For Integrated Circuit
Granted: October 8, 2009
Application Number:
20090250805
A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically…
Posted Memory Write Verification
Granted: October 1, 2009
Application Number:
20090248942
A method for verifying the proper communication of data packets from an initiator device on a PCIe data bus to a target device on the data bus. A target-specific counter on the initiator is synchronized to an initiator-specific counter on the target with the same value. The initiator writes the value of the target-specific counter into the tag field of the packet header, and also writes an identifier of the initiator into the header. Then the initiator sends the packet to the target on…
Raid Error Recovery Logic
Granted: October 1, 2009
Application Number:
20090249111
A method of reading desired data from drives in a RAID1 data storage system, by determining a starting address of the desired data, designating the starting address as a begin read address, designating one of the drives in the data storage system as the current drive, and iteratively repeating the following steps until all of the desired data has been copied to a buffer: (1) reading the desired data from the current drive starting at the begin read address and copying the desired data…
METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE
Granted: September 24, 2009
Application Number:
20090236668
The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe…
WIRE BONDING OVER ACTIVE CIRCUITS
Granted: September 24, 2009
Application Number:
20090236742
A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.
