ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS
Granted: May 28, 2015
Application Number:
20150149698
Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the…
INCREMENTAL UPDATES FOR ORDERED MULTI-FIELD CLASSIFICATION RULES WHEN REPRESENTED BY A TREE OF LONGEST PREFIX MATCHING TABLES
Granted: May 28, 2015
Application Number:
20150149395
An apparatus includes a memory and a processor. The memory may be configured to store at least a portion of a multi-level tree representation of an ordered multi-field rule-based classification list. The tree representation includes at least one non-leaf level and one or more leaf levels. Each entry in the at least one non-leaf level contains a count value indicating a number of rules having a matching field. Entries in at least one of the one or more leaf levels include rule pointers…
Integrated Frequency Multiplier and Slot Antenna
Granted: May 28, 2015
Application Number:
20150145740
A metal substrate with a slot therein forms a slot antenna, the slot having a major axis and a minor axis. A dielectric layer has a plurality of terminals disposed on or in the dielectric layer and the layer is attached on one surface of the substrate. The terminals of a non-linear device, such as a diode, are connected to corresponding terminals of the dielectric layer. The non-linear device is positioned proximate the slot and is substantially aligned with a minor axis of the slot. A…
Current To Voltage Converter
Granted: May 21, 2015
Application Number:
20150137855
An apparatus for converting current to voltage includes a pair of current inputs, a differential voltage output connected to the pair of current inputs, a current summing node connected to the pair of current inputs through a first resistor branch, a common mode feedback node connected to the pair of current inputs through a second resistor branch, an amplifier operable to generate a current control signal based at least in part on a voltage at the common mode feedback node, and a…
Systems and Methods for Soft Decision Generation in a Solid State Memory System
Granted: May 21, 2015
Application Number:
20150143202
Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.
Systems and Methods for FAID Follower Decoding
Granted: May 21, 2015
Application Number:
20150143196
Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information.
I/O REQUEST MIRRORING IN A CLUSTERED STORAGE SYSTEM
Granted: May 21, 2015
Application Number:
20150143164
Clustered storage systems and methods are presented herein. One clustered storage system includes a logical volume comprising first and second pluralities of storage devices. The first plurality of storage devices is different from the second plurality of storage devices and includes at least the same data as the second plurality of devices. The storage system also includes a first storage node operable to process first I/O requests to the first plurality of storage devices and a second…
GLOBAL BITLINE WRITE ASSIST FOR SRAM ARCHITECTURES
Granted: May 21, 2015
Application Number:
20150138876
An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at…
MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES
Granted: May 21, 2015
Application Number:
20150138864
Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected…
INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES
Granted: May 21, 2015
Application Number:
20150138863
An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first…
Detection/Erasure of Random Write Errors Using Converged Hard Decisions
Granted: May 14, 2015
Application Number:
20150135032
A low-density parity-check decoder in a system with multi-level cells identifies zones of reliability where write errors or stuck cells are identifiable. The system uses assumedly successfully decoded pages associated with bits in a cell to identify candidate write errors or stuck cells and erases a corresponding log-likelihood ratio even where such log-likelihood ratio is saturated, thereby breaking a potential trapping set without post-processing.
DYNAMIC PER-DECODER CONTROL OF LOG LIKELIHOOD RATIO AND DECODING PARAMETERS
Granted: May 14, 2015
Application Number:
20150135031
An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control…
System and Method of Write Hole Protection for a Multiple-Node Storage Cluster
Granted: May 14, 2015
Application Number:
20150135006
The disclosure is directed to preserving data consistency in a multiple-node data storage system. According to various embodiments, a write log is maintained including log entries for data transfer requests being served by a respective node of the multiple-node data storage system. Rather than maintaining a full write journal of data and parity associated with each data transfer request, the log entries only need to identify portions of the virtual volume being updated according to the…
Decoupling Host and Device Address Maps for a Peripheral Component Interconnect Express Controller
Granted: May 14, 2015
Application Number:
20150134855
A controller includes a virtual memory mapped to device-side Peripheral component interconnect express address space includes virtual buffers allocation for each data transfer. Each virtual buffer is associated with a scatter/gather list entry in a host memory. The controller executes direct transfers between Peripheral component interconnect express devices and host memory without introducing address mapping dependencies between the host and device domains.
Systems and Methods for Lost Synchronization Data Set Reprocessing
Granted: May 14, 2015
Application Number:
20150134613
Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set.
Incremental Programming Pulse Optimization to Reduce Write Errors
Granted: May 14, 2015
Application Number:
20150131373
In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate…
DEVICE QUALITY METRICS USING UNSATISFIED PARITY CHECKS
Granted: May 7, 2015
Application Number:
20150128006
An apparatus having a device and a circuit is disclosed. The device is configured to convey a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword, (iii) generate a value by counting a number of unsatisfied parity checks in the syndrome and (iv) generate a quality metric of the device according to the value.
REDUCTION OR ELIMINATION OF A LATENCY PENALTY ASSOCIATED WITH ADJUSTING READ THRESHOLDS FOR NON-VOLATILE MEMORY
Granted: May 7, 2015
Application Number:
20150127883
Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is…
METHOD AND SYSTEM FOR SESSION BASED DATA MONITORING FOR WIRELESS EDGE CONTENT CACHING NETWORKS
Granted: April 30, 2015
Application Number:
20150117226
Aspects of the disclosure pertain to methods and systems that are configured to monitor data usage at a network edge. In an implementation, a method includes monitoring data usage information associated with a mobile user session between a mobile device and a plurality of edges nodes of a communication network, where the plurality of edge nodes includes at least a beginning edge node and a final edge node. The method also includes storing data usage information from the monitored data…
Data Interface for Point-to-Point Communications Between Devices
Granted: April 30, 2015
Application Number:
20150120981
A data interface is provided for point-to-point communications between two devices, such as a read channel and a disk controller in an HDD system. An interface for communications from a transmitting device to a receiving device comprises a data bus configured to communicate m bits of data and a corresponding n bit data tag, wherein a given n bit data tag identifies a data type of a corresponding m bits of data on the data bus. An acknowledge signal from the receiving device optionally…
