Task backpressure and deletion in a multi-flow network processor architecture
Granted: December 9, 2014
Patent Number:
8910168
Described embodiments generate tasks corresponding to packets received by a network processor. A source processing module sends task messages including a task identifier and a task size to a destination processing module. The destination module receives the task message and determines a queue in which to store the task. Based on a used cache counter of the queue and a number of cache lines for the received task, the destination module determines whether the queue has reached a usage…
Systems and methods for selective retry data retention processing
Granted: December 9, 2014
Patent Number:
8910005
Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for re-processing data sets not successfully processed during standard processing.
Begin anchor annotation in DFAs
Granted: December 9, 2014
Patent Number:
8909672
Disclosed is a method and system of matching a string of symbols to a ruleset. The ruleset comprise a set of rules. The method includes ignoring begin anchor requirements when constructing a DFA from all the rules of the ruleset, annotating the accepting states of the DFA with the begin anchor information, executing the DFA, and checking begin anchor annotations to determine if begin anchor requirement are satisfied if an accepting state is reached. Embodiments also include rulesets with…
Receiver with distortion compensation circuit
Granted: December 9, 2014
Patent Number:
8908816
A receiver containing analog circuitry that generates distortion, a distortion compensation circuit coupled to an output of the analog circuitry, and a slicer, operating as a signal peak detector, coupled to the distortion compensation circuitry. The distortion compensation circuit has a subtractor, a function generator, and a weighting circuit. The subtractor has a first input coupled to the output of the analog circuitry, a second input, and an output. The function generator has an…
Hybrid digital/analog power amplifier
Granted: December 9, 2014
Patent Number:
8908798
The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance…
Shared threshold/undershoot laser output driver
Granted: December 9, 2014
Patent Number:
8908730
A laser driver apparatus, system, and method include a single laser driver. One or more threshold levels and one or more undershoot levels can be digitally combined into a single output with respect to the single laser driver to reduce the output capacitance of the single laser driver and minimize circuit power, resulting in a faster and higher fidelity signal thereof. A decoder (e.g., thermometer decoding) can also be provided, wherein the threshold level(s) and the undershoot level(s)…
Systems and methods for hard disk drive region based data encoding
Granted: December 9, 2014
Patent Number:
8908307
Systems and method relating generally to improving usage of storage area on a disk drive, and more particularly to systems and methods for applying encoding based upon the nature of a particular region of a disk platter on the disk drive.
Systems and methods for slider head stability determination
Granted: December 9, 2014
Patent Number:
8908305
Systems and method relating generally to data processing, and more particularly to systems and methods for determining head stability.
Systems and methods for channel target based CBD estimation
Granted: December 9, 2014
Patent Number:
8908304
Various approaches, methods, systems, circuits and devices for channel bit density estimation.
Integrated circuit having clock gating circuitry responsive to scan shift control signal
Granted: December 2, 2014
Patent Number:
8904255
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock…
Arbitration circuitry for asynchronous memory accesses
Granted: December 2, 2014
Patent Number:
8904221
A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in…
Storage system with boot appliance for improving reliability/availability/serviceability in high density server environments
Granted: December 2, 2014
Patent Number:
8904158
The present invention is directed to a boot appliance for a data storage system. The boot appliance is a self-contained, pre-configured device that serves as a boot device for multiple servers. The boot appliance contains multiple hard drives which are configured into one or more RAID volumes. Each volume is divided into multiple partitions, with each partition serving as the boot drive for any server connected to it. The boot appliance provides its own environmental controls and…
Merging a storage cluster into another storage cluster
Granted: December 2, 2014
Patent Number:
8904141
A method for merging a source electronic memory storage cluster into a destination electronic memory storage cluster may include designating a source storage cluster having a first configuration; designating a destination storage cluster having a second configuration; receiving a configuration database including mapping information associated with the first configuration of the source storage cluster; merging the configuration database for the source storage cluster into the destination…
Methods and structure establishing nested Redundant Array of Independent Disks volumes with an expander
Granted: December 2, 2014
Patent Number:
8904108
Methods and structure are provided for provisioning a Redundant Array of Independent Disks (RAID) volume via an expander that can be used to provision a RAID volume managed by an external RAID controller. The structure includes a Serial Attached SCSI (SAS) expander. The expander comprises physical links with transceivers (PHYs) that directly couple with storage devices, a protocol target and a control unit. The control unit provisions a first RAID volume with multiple storage devices…
Systems and methods for digital MRA compensation
Granted: December 2, 2014
Patent Number:
8904070
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a…
System and method for determining channel loss in a dispersive communication channel at the Nyquist frequency
Granted: December 2, 2014
Patent Number:
8902959
The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver…
Skew-tolerant reader configurations using cross-track profiles for array-reader based magnetic recording
Granted: December 2, 2014
Patent Number:
8902536
A method for enhancing read performance in an ARMR system includes: obtaining a first reader offset profile corresponding to a first reader of a multi-reader array head in the ARMR system; obtaining at least a second reader offset profile corresponding to at least a second reader of the multi-reader array head in the ARMR system; combining the first and second reader offset profiles to generate a combined reader offset profile; and controlling a location of the multi-reader array head in…
Systems and methods for indirect parameter calibration in a data processing system
Granted: December 2, 2014
Patent Number:
8902525
The present invention is related to systems and methods for adaptive parameter modification in a data processing system.
Inter-track interference mitigation in magnetic recording systems using averaged values
Granted: December 2, 2014
Patent Number:
8902524
Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems using averaged values. Inter-track interference (ITI) is mitigated in a magnetic recording system by obtaining ITI cancellation data; and providing the ITI cancellation data for ITI mitigation, wherein the ITI mitigation is performed in combination with an averaging procedure for one or more of ITI mitigation of averaged data and averaging of ITI mitigated data. The…
Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment
Granted: November 25, 2014
Patent Number:
8898361
Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt…
