Systems and methods for loop processing with variance adaptation
Granted: December 30, 2014
Patent Number:
8922933
Systems and methods for data processing, and more particularly systems and methods for loop processing with variance adaptation.
Optimization of data processors with irregular patterns
Granted: December 30, 2014
Patent Number:
8923413
In described embodiments, data streams with irregular patterns are processed by transformations defined by recursively changing processor state, or iteration level. The data transformations are applied to an arbitrary long portion of data, instead of small portions, that are defined directly by a current processor state. Embodiments combine small parts of, for example, puncturing/repetition patterns into a pattern of bigger parts and apply these patterns of bigger parts to relatively…
Tap adaptation with a fully unrolled decision feedback equalizer
Granted: December 30, 2014
Patent Number:
8923382
Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators,…
SerDes data sampling gear shifter
Granted: December 30, 2014
Patent Number:
8923371
A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the…
Packet router having a hierarchical buffer structure
Granted: December 30, 2014
Patent Number:
8923315
A packet-router architecture in which buffer modules are interconnected by one or more interconnect fabrics and arranged to form a plurality of hierarchical buffer levels, with each higher buffer level having more buffer modules than a corresponding lower buffer level. An interconnect fabric is configured to connect three or more respective buffer modules, with one of these buffer modules belonging to one buffer level and the other two or more buffer modules belonging to a next higher…
Address decoding circuits for reducing address and memory enable setup time
Granted: December 30, 2014
Patent Number:
8923090
A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a…
Single-port read multiple-port write storage device using single-port memory cells
Granted: December 30, 2014
Patent Number:
8923089
A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The…
Method and apparatus for decreasing leakage power consumption in power gated memories
Granted: December 30, 2014
Patent Number:
8923087
A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select…
Memory having self-timed edge-detection write tracking
Granted: December 30, 2014
Patent Number:
8923069
A memory includes a self-timed column imitating a bitline loading, a self-timed row imitating a self-timed word-line, a self-timed bitcell performing a dummy write in a write cycle, a writer driver coupled to the self-timed bitcell for an actual write, and an edge detection circuit coupled to the self-timed bitcell for tracking a write cycle time.
Systems and methods for transition based equalization
Granted: December 30, 2014
Patent Number:
8922934
Systems, methods, devices, circuits for transition based equalization.
Peak current controlled switching voltage regulator system and method for providing a self power down mode
Granted: December 30, 2014
Patent Number:
8922191
A peak current controlled switching voltage regulator system and method for providing a self-power down mode. An on-chip voltage regulator integrated into an on-chip digital logic circuit provides a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor. An off-chip regulator connected to the on-chip digital logic circuit provides an external core supply voltage with respect to the on-chip digital logic circuit. A start-up circuit operates the on-chip…
SAS expander and method to arbitrate traffic in a redundant expander system
Granted: December 23, 2014
Patent Number:
8918557
A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.
Method and apparatus for controlling buffer overflow in a communication system
Granted: December 23, 2014
Patent Number:
8917797
A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. An audio encoder marks a frame as “dropped” whenever a buffer overflow might occur. Only a small number of bits are utilized to process a lost frame, thereby preventing the buffer from overflowing and allowing the encoder buffer-level to quickly recover from the potential overflow condition. The audio encoder optionally sets a flag that provides an indication to…
Multicasting traffic manager in a network communications processor architecture
Granted: December 23, 2014
Patent Number:
8917738
Described embodiments provide a method of processing packets of a network processor. One or more tasks are generated corresponding to received packets associated with one or more data flows. A traffic manager receives a task corresponding to a data flow, the task provided by a processing module of the network processor. The traffic manager determines whether the received task corresponds to a unicast data flow or a multicast data flow. If the received task corresponds to a multicast data…
Data sequence detection in band-limited channels using cooperative sequence equalization
Granted: December 23, 2014
Patent Number:
8917470
A method for detecting a data sequence includes generating a sample stream, which is a time-sequenced digital signal associated with samples of an analog signal. The sample stream is input to n equalization filter banks, which each have m equalization filters to generate m equalized sample streams. The m equalized sample streams from each equalization filter bank are input to a corresponding one of n noise predictive filters. Each noise predictive filter is an m-tap noise predictive…
Systems and methods for media defect detection with pattern qualification
Granted: December 23, 2014
Patent Number:
8917468
An apparatus for detecting media flaws includes an envelope based media defect detector operable to identify a media defect based on an envelope of an input signal, a periodic pattern detector operable to determine whether the input signal comprises a data pattern, and a media flaw signal generation circuit operable to indicate a media defect when the envelope based media defect detector identifies the media defect and the periodic pattern detector determines that the input signal does…
Systems and methods for ATI mitigation
Granted: December 23, 2014
Patent Number:
8917467
Systems, methods, devices, circuits for data processing, and more particularly to data processing including adjacent track interference mitigation.
Systems and methods for governing in-flight data sets in a data processing system
Granted: December 23, 2014
Patent Number:
8917466
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for governing a data processing system.
Systems and methods for adaptive gain control
Granted: December 16, 2014
Patent Number:
8913339
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, a data detector circuit, a filter circuit, an error generation circuit, and a target parameter adaptation circuit. The analog to digital converter circuit converts an analog input into corresponding digital samples. The data detector circuit applies a data detection algorithm to a data set…
Systems and methods for hard disk drive region based data encoding
Granted: December 9, 2014
Patent Number:
8908307
Systems and method relating generally to improving usage of storage area on a disk drive, and more particularly to systems and methods for applying encoding based upon the nature of a particular region of a disk platter on the disk drive.
