Offset-tolerant low noise amplifier
Granted: January 6, 2015
Patent Number:
8929012
The disclosure is directed to a low noise amplifier (LNA) configuration that compensates for DC offsets of incoming signals from a magnetoresistive head. According to various embodiments, the LNA includes a shunt-feedback differential pair of amplifiers adaptively biased according to a detected input DC voltage offset of the incoming signals from the magnetoresistive head. The LNA is thus enabled to amplify the AC signal component substantially unaffected by the DC offset. The DC…
Method and apparatus for iterative error-erasure decoding
Granted: January 6, 2015
Patent Number:
8930797
Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A…
Error injection for LDPC retry validation
Granted: January 6, 2015
Patent Number:
8930794
The present inventions are related to systems and methods for validating retry features in LDPC decoders and in systems incorporating LDPC decoders. For example, a data processing circuit is disclosed that includes a low density parity check decoder and is operable to correct errors in a data set. The data processing circuit includes at least one retry feature operable to assist in correcting the errors that are not corrected without the at least one retry feature. A retry validation…
Systems and methods for distributed low density parity check decoding
Granted: January 6, 2015
Patent Number:
8930792
Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data…
LDPC decoder with fractional unsatisfied check quality metric
Granted: January 6, 2015
Patent Number:
8930788
An apparatus includes a low density parity check decoder operable to iteratively generate messages between a plurality of check nodes and variable nodes, and to calculate a fractional quality metric for a data block as it is decoded in the low density parity check decoder based at least in part on perceived values of data in the variable nodes. The fractional unsatisfied check quality metric is a probabilistic determination of a number of unsatisfied parity checks in the low density…
Systems and methods for non-zero syndrome based processing
Granted: January 6, 2015
Patent Number:
8930780
The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set…
Ordering a plurality of write commands associated with a storage device
Granted: January 6, 2015
Patent Number:
8930606
A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.
Reliable notification of interrupts in a network processor by prioritization and policing of interrupts
Granted: January 6, 2015
Patent Number:
8930604
In a data network, a node determines whether to handle data-dependent events using the node's hardware interrupt buffer or instead using an available fallback action. The node classifies each detected event as being one of a plurality of different categories of events and determines, based on the classified category, whether to handle the detected event using the hardware interrupt buffer of the node. Each different event category can be assigned its own scale factor, where the available…
Dynamic deskew for bang-bang timing recovery in a communication system
Granted: January 6, 2015
Patent Number:
8929497
Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled that iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive…
Systems and methods for SNR measurement using equalized data
Granted: January 6, 2015
Patent Number:
8929017
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an equalizer circuit, a signal to noise ratio calculation circuit, and a parameter adjustment circuit. The equalizer circuit is operable to equalize a data input to yield an equalized output. The signal to noise ratio calculation circuit is operable to calculate a signal to noise ratio of the equalized output based at least in…
Sync mark system for two dimensional magnetic recording
Granted: January 6, 2015
Patent Number:
8929011
A data processing system includes an analog to digital converter operable to sample an analog signal obtained from a magnetic storage medium to yield digital samples, and a sync mark detector operable to search for a particular one of a number of sync marks in the digital samples. Each of the data tracks on the magnetic storage medium is associated with one of the sync marks. The sync mark on each of the data tracks has a different pattern than the sync marks on neighboring tracks.
Peak current controlled switching voltage regulator system and method for providing a self power down mode
Granted: December 30, 2014
Patent Number:
8922191
A peak current controlled switching voltage regulator system and method for providing a self-power down mode. An on-chip voltage regulator integrated into an on-chip digital logic circuit provides a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor. An off-chip regulator connected to the on-chip digital logic circuit provides an external core supply voltage with respect to the on-chip digital logic circuit. A start-up circuit operates the on-chip…
Half-duplex speakerphone echo canceler
Granted: December 30, 2014
Patent Number:
8923508
A speakerphone having transmit path with a microphone and a first amplifier having a gain determined by a controller and an input coupled to the microphone, a receive path with a second amplifier having a gain determined by the controller and a speaker coupled to an output of the second amplifier, and operable in a half-duplex mode using an adaptive echo canceller to at least partially remove from the transmit path acoustically-coupled signals from the receive path. The controller…
Tap adaptation with a fully unrolled decision feedback equalizer
Granted: December 30, 2014
Patent Number:
8923382
Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators,…
SerDes data sampling gear shifter
Granted: December 30, 2014
Patent Number:
8923371
A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the…
Packet router having a hierarchical buffer structure
Granted: December 30, 2014
Patent Number:
8923315
A packet-router architecture in which buffer modules are interconnected by one or more interconnect fabrics and arranged to form a plurality of hierarchical buffer levels, with each higher buffer level having more buffer modules than a corresponding lower buffer level. An interconnect fabric is configured to connect three or more respective buffer modules, with one of these buffer modules belonging to one buffer level and the other two or more buffer modules belonging to a next higher…
Address decoding circuits for reducing address and memory enable setup time
Granted: December 30, 2014
Patent Number:
8923090
A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a…
Single-port read multiple-port write storage device using single-port memory cells
Granted: December 30, 2014
Patent Number:
8923089
A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The…
Systems and methods for transition based equalization
Granted: December 30, 2014
Patent Number:
8922934
Systems, methods, devices, circuits for transition based equalization.
Systems and methods for loop processing with variance adaptation
Granted: December 30, 2014
Patent Number:
8922933
Systems and methods for data processing, and more particularly systems and methods for loop processing with variance adaptation.
